Semiconductor device manufacturing: process – Repair or restoration
Reexamination Certificate
2007-11-01
2010-11-30
Landau, Matthew C (Department: 2813)
Semiconductor device manufacturing: process
Repair or restoration
C438S409000, C438S778000, C438S791000, C257SE21001, C257SE21273
Reexamination Certificate
active
07842518
ABSTRACT:
A method for fabricating a semiconductor device, includes forming a porous dielectric film above a substrate using a porous insulating material, forming an opening in the porous dielectric film, repairing film quality of the porous dielectric film on a surface of the opening by feeding a predetermined gas replacing a Si—OH group to the opening, and performing pore sealing of the surface of the opening using the same predetermined gas as that used for film quality repairs after repairing the film quality.
REFERENCES:
patent: 6855645 (2005-02-01), Tang et al.
patent: 2005/0287790 (2005-12-01), Owada et al.
patent: 2007/0037374 (2007-02-01), Hayashi et al.
patent: 2007/0249156 (2007-10-01), Bonilla et al.
patent: 2009/0017563 (2009-01-01), Jiang et al.
patent: 2002-353308 (2002-12-01), None
patent: 2006-073799 (2006-03-01), None
patent: 2006-114719 (2006-04-01), None
Nakamura, N. et al., “A Plasma Damage Resistant Ultra Low-k Hybrid Dielectric Structure for 45nm Node Copper Dual-Damascene Interconnects,” Proceeding of the IEEE 2004 International Interconnect Technology Conference, pp. 228-230, (Jun. 7-9, 2004).
Kojima, A. et al., “Silylation Gas Restoration Subsequent to All-in-one RIE Process without Air Exposure for Porous Low-k SiOC/Copper Dual-Damascene Interconnects,” Advanced Metallization Conference 2006, (AMC 2006), Conference Proceedings AMC XXII, Materials Research Society, pp. 301-305, (2007).
Nakamura, N. et al., “Impact of Damage Restoration Process on electrical Properties and Reliability of Porous Low-k SiOC/Copper Dual-Damascene Interconnects,” Advanced Metallization Conference 2005, (AMC 2005), Conference Proceedings AMC XXI, Materials Research Society, pp. 707-713, (2006).
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Landau Matthew C
Snow Colleen E
LandOfFree
Method for fabricating semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4208382