Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2007-02-20
2007-02-20
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C438S704000, C438S706000, C438S745000, C252S079100, C252S079400
Reexamination Certificate
active
10617182
ABSTRACT:
A method for fabricating a semiconductor device includes the steps of: (a) forming a plurality of conductive patterns on a substrate in a cell region and a peripheral circuit region; (b) forming an insulation layer on an entire surface of the resulting structure from the step. (a); (c) forming a plurality of plugs in the cell region and simultaneously forming a dummy pattern in a region between the cell region and the peripheral circuit region, each plug and the dummy pattern being contacted to the substrate allocated between the conductive patterns by passing through the insulation layer; (d) forming a photoresist pattern masking the resulting structure in the cell region; and (e) removing the insulation layer in the peripheral circuit region by performing a wet etching process with use of the photoresist pattern as an etch mask to thereby expose a surface of the substrate in the peripheral circuit region.
REFERENCES:
patent: 6458655 (2002-10-01), Yuzuriha et al.
patent: 6531758 (2003-03-01), Shin et al.
patent: 6573168 (2003-06-01), Kim et al.
patent: 1020020054677 (2002-07-01), None
patent: 1020020054678 (2002-07-01), None
Kim Sang-Ik
Lee Min-Suk
Lee Sung-Kwon
Hynix / Semiconductor Inc.
Mayer Brown Rowe & Maw LLP
Norton Nadine G.
Umez-Eronini Lynette T.
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