Method for fabricating semiconductor device

Details Method for fabricating semiconductor device Method for fabricating semiconductor device

2006-05-30

2006-05-30

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S634000, C438S672000, C438S720000

Reexamination Certificate

active

07052999

ABSTRACT:
The present invention provides a method for fabricating a semiconductor device capable of decreasing a parasitic capacitance to thereby increase a cell capacitance. To achieve this effect, the deposited third inter-layer insulation layer is planarized and is subjected to a wet etching process to make its height lower than that of the bit line. Afterwards, the nitride-based etch stop layer is formed on the etched third inter-layer insulation layer, and then, the contact hole for forming the storage node contact plug is formed in between the bit lines through the SAC process so that the etch stop layer does not remain at sidewalls of the bit line. From this structure, it is possible to decrease the parasitic capacitance, and this decrease further provides an effect of increasing the cell capacitance.

REFERENCES:
patent: 6074959 (2000-06-01), Wang et al.
patent: 6183655 (2001-02-01), Wang et al.
patent: 6277727 (2001-08-01), Kuo et al.
patent: 6287957 (2001-09-01), Linliu
patent: 6448179 (2002-09-01), Kim et al.
patent: 03-248537 (1991-11-01), None

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