Method for fabricating semiconductor device

Details Method for fabricating semiconductor device Method for fabricating semiconductor device

2005-05-24

2005-05-24

Goudreau, George A. (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S723000, C438S724000, C438S734000, C438S740000

Reexamination Certificate

active

06897159

ABSTRACT:
Disclosed is a method for fabricating a semiconductor device having at least one contact holes formed by employing a self-aligned contact (SAC) etching process. The contact holes are formed through the shortened number of sequential steps by using different process recipes. First, an anti-reflective coating (ARC) layer formed on a substrate structure prepared sequentially with a substrate, conductive structures, an etch stop layer and an inter-layer insulation layer is etched by employing an etch gas of CF4, O2, CO and Ar. Then, a portion of an inter-layer insulation layer is etched with use of an etch gas of CF4and O2. The rest portion of the inter-layer insulation layer is subsequently etched by using a different etch gas of C4F6, CH2F2, O2and Ar to thereby form at least one contact hole exposing the etch stop layer.

REFERENCES:
patent: 6362109 (2002-03-01), Kim et al.
patent: 6518164 (2003-02-01), Wu et al.
patent: 6569778 (2003-05-01), Lee et al.
patent: 20010005634 (2001-06-01), Kajiwara
patent: 20030181054 (2003-09-01), Lee et al.

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