Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-07-29
2004-08-24
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S725000, C438S740000
Reexamination Certificate
active
06780778
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, in which a plug or inlaid interconnect is formed by a single or dual damascene process.
Recently, various methods of forming an inlaid interconnect for a semiconductor device by a single or dual damascene process have been researched and developed.
Hereinafter, a known method of fabricating a semiconductor device by a single damascene process (which will be herein called a “first prior art example” for convenience sake) will be described with reference to FIGS.
20
(
a
) through
20
(
d
).
First, as shown in FIG.
20
(
a
), an insulating film
11
, which may be either an SiO
2
film or a film with a dielectric constant lower than that of an SiO
2
film, is deposited over a semiconductor substrate
10
. Next, as shown in FIG.
20
(
b
), an etch stopper film
12
with insulation properties, which may be an Si
3
N
4
film, for example, is deposited over the insulating film
11
.
Then, as shown in FIG.
20
(
c
), a resist pattern
13
is defined on the etch stopper film
12
. And the insulating film
11
is plasma-etched using the resist pattern
13
as a mask, thereby forming an opening
14
that passes through the stopper and insulating films
12
and
11
as shown in FIG.
20
(
d
). The opening
14
will be used as a via hole or interconnection groove. If the resist pattern
13
disappears as a result of the plasma etching process, then the etch stopper film
12
will be a hard mask.
Subsequently, the resist pattern
13
is stripped by an ashing process using oxygen plasma, and then the inner faces of the opening
14
are cleaned. Thereafter, although not shown, a metal film is deposited over the substrate to fill in the opening
14
and then parts of the metal film, which are exposed on the stopper film
12
, are removed by a chemical/mechanical polishing (CMP) process, for example. In this manner, a plug or inlaid interconnect is formed inside the opening
14
.
Hereinafter, another known method of fabricating a semiconductor device by a dual damascene process (which will be herein called a “second prior art example” for convenience sake) will be described with reference to FIGS.
21
(
a
) through
21
(
d
) and
22
(
a
) through
22
(
c
).
First, as shown in FIG.
21
(
a
), a first insulating film
21
, which may be either an SiO
2
film or a film with a dielectric constant lower than that of an SiO
2
film, is deposited over a semiconductor substrate
20
. Next, a first etch stopper film
22
with insulation properties, which may be an Si
3
N
4
film, for example, is deposited over the first insulating film
21
.
Then, as shown in FIG.
21
(
b
), a second insulating film
23
, which may be either an SiO
2
film or a film with a dielectric constant lower than that of an SiO
2
film, is deposited over the first etch stopper film
22
. Next, as shown in FIG.
21
(
c
), a second etch stopper film
24
with insulation properties, which may be an Si
3
N
4
film, for example, is deposited over the second insulating film
23
.
Subsequently, as shown in FIG.
21
(
d
), a first resist pattern
25
with an opening
25
a
for via hole is defined on the second etch stopper film
24
. And the second etch stopper film
24
, second insulating film
23
, first etch stopper film
22
and first insulating film
21
are plasma-etched using the first resist pattern
25
as a mask, thereby forming a via hole
26
as shown in FIG.
22
(
a
).
Thereafter, as shown in FIG.
22
(
b
), a second resist pattern
27
with an opening
27
a
for interconnection groove is defined on the second stopper film
24
. And the second etch stopper film
24
and second insulating film
23
are plasma-etched using the second resist pattern
27
as a mask, thereby forming an interconnection groove
28
as shown in FIG.
22
(
c
). Subsequently, the second resist pattern
27
is stripped by an ashing process using oxygen plasma, and then the inner faces of the via hole
26
and interconnection groove
28
are cleaned.
Then, although not shown, a metal film is deposited over the substrate to fill in the via hole
26
and interconnection groove
28
and then parts of the metal film, which are exposed on the second etch stopper film
24
, are removed by a CMP process, for example. In this manner, a dual damascene metallization structure is obtained.
The single damascene process of the first prior art example, however, has the following drawbacks. Specifically, when the resist pattern
13
is stripped by the ashing process using oxygen plasma, a damaged layer
15
is formed by the oxygen plasma on the inner walls of the insulating film
11
(i.e., parts the film
11
surrounding the opening
14
) as shown in FIG.
23
(
a
). In addition, the insulating film
11
is deformed and partially lost. In other words, the inner walls of the opening
14
in the insulating film
11
are dented inward unintentionally. As a result, the diameter (or diameter) of the opening
14
exceeds a predetermined value, i.e., the diameter of the opening of the etch stopper film
12
.
To eliminate the process step of stripping the resist pattern
13
by the ashing process using the oxygen plasma, the resist pattern
13
may be removed by over-etching the insulating film
11
in the plasma etching process.
However, if the insulating film
11
is over-etched, then the following problems will newly arise.
First, if the insulating film
11
is either an inorganic insulating film or an organic/inorganic hybrid film, a CFC etching gas is normally used to plasma-etch the insulating film
11
. Thus, if the over-etching process is performed for a long time, then a Teflon (polytetrafluoroethylene) film is formed on the inner walls of the opening
14
. In that case, an ashing process should be performed for a long time or intensely to remove the Teflon film.
As a result of such an intense ashing process, a damaged layer will be formed in the insulating film
11
, e.g., on the inner walls or on the bottom of the opening
14
, or the insulating film
11
will be partially deformed. For example, the inner walls of the opening
14
might be partially etched away and deformed into a bowed shape. Particularly when the insulating film
11
is an organic/inorganic hybrid film, the damaged layer, which will be formed around the opening
14
of the insulating film
11
, adversely increases the dielectric constant.
Next, if the insulating film
11
is an organic insulating film, then the insulating film
11
is normally plasma-etched using a gas containing oxygen or a mixture of nitrogen and hydrogen gases as the etching gas. However, if the over-etching process is performed for a long time using a gas containing oxygen as the etching gas, then the insulating film
11
will be partially deformed (i.e., the inner walls of the opening
14
will be dented inward). Or the damaged layer will be formed around the inner walls of the opening
14
to increase the dielectric constant unintentionally. On the other hand, if a mixture of nitrogen and hydrogen gases is used as the etching gas, then normally the inner walls of the opening
14
will not be dented so much as the process where the oxygen-containing gas is used. However, if the over-etching process is performed for a long time, then the insulating film
11
will also be partially deformed (i.e., the inner walls of the opening
14
will also be dented noticeably) or the damaged layer will also be formed around the inner walls of the opening
14
. In addition, reactants (i.e., etching residue) will be deposited on the bottom of the opening
14
. Accordingly, if the over-etching is performed for a rather long time, then the ashing process will also be needed, thus causing deformation or damage as well.
Considering these potential disadvantages, it is not preferable to over-etch the insulating film
11
for the purpose of eliminating the ashing process using the oxygen plasma.
The same problems arise in the dual damascene process of the second prior art example, too. Specifically, when the second resist pattern
27
is s
Nakagawa Hideo
Tamaoka Eiji
Chen Kin-Chan
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Studebaker Donald R.
LandOfFree
Method for fabricating semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3306692