Method for fabricating semiconductor circuits

Details Method for fabricating semiconductor circuits Method for fabricating semiconductor circuits

1992-07-10

1994-07-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437195, 437 51, 437 48, H01L 2144

Patent

active

053309332

ABSTRACT:
A method for fabricating a resistive load element for a semiconductor device can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is then patterned to define conductors and resistive load elements. The resistive load elements are formed by back-to-back PN diodes formed at the interfaces between the P-type and N-type regions.

REFERENCES:
patent: 4178674 (1979-12-01), Liu et al.
patent: 4180826 (1979-12-01), Shappir
patent: 4505026 (1985-03-01), Bohr et al.
patent: 4619037 (1986-10-01), Taguchi et al.
patent: 4877483 (1989-10-01), Bergemont et al.
patent: 4950620 (1990-08-01), Harrington, III
patent: 4966864 (1990-10-01), Pfiester
patent: 5151376 (1992-09-01), Spinner, III
patent: 5187114 (1993-02-01), Chan et al.

Affiliated with

Also associated with

Rating

Method for fabricating semiconductor circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating semiconductor circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating semiconductor circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-519767