Method for fabricating self-aligning mask layers

Details Method for fabricating self-aligning mask layers Method for fabricating self-aligning mask layers

2002-07-22

2004-09-21

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

C438S248000, C438S437000, C438S445000

Reexamination Certificate

active

06794259

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for fabricating self-aligning mask layers and, in particular, to a method for fabricating an undensified conformal mask layer that has different etching rates or a self-aligning etching-back on account of a different mechanical stress.
To elucidate the invention, the latter is described using a method for fabricating a trench capacitor, as is used in semiconductor memory cells of integrated semiconductor circuits. However, the invention can be applied in the same way generally to microelectronic, micromechanical, and also combinations of microelectronic and micromechanical systems with such self-aligning etching-back.
To illustrate the present invention, firstly a description is given of a conventional method for fabricating a trench capacitor in a dynamic semiconductor memory cell of a dynamic memory DRAM.
FIG. 1
shows a conventional trench capacitor as is used, in particular, in a DRAM semiconductor memory cell and is disclosed in U.S. Pat. No. 5,945,704 to Schrems et al., for example. Such a DRAM semiconductor memory cell substantially includes a capacitor
160
, which is formed in a substrate
101
. The substrate
101
is lightly doped, for example, with p-type dopants such as boron, for example. A trench is usually filled with polysilicon
161
, which is heavily n
+
-doped with arsenic or phosphorus, for example. A buried plate
165
doped with arsenic, for example, is situated in the substrate
101
at a lower region of the trench. The arsenic or the dopant is usually diffused into the silicon substrate
101
from a dopant source such as, e.g., an arsenosilicate glass ASG formed at the sidewalls of the trench. In this case, the polysilicon
161
and the buried plate
165
serve as electrodes of the capacitor
160
, a dielectric layer
164
separating the electrodes of the capacitor from one another.
The DRAM semiconductor memory cell in accordance with
FIG. 1
furthermore has a field-effect transistor
110
. The transistor
110
, usually referred to as a selection transistor, has a gate
112
and diffusion regions
113
and
114
as source and drain. The diffusion regions, which are spaced apart from one another by a channel
117
, are usually formed by the implantation of dopants such as, e.g., phosphorus. Furthermore, a contact diffusion region
125
is formed in the semiconductor substrate
101
, which connects the capacitor
160
to the selection transistor
110
through, for example, a further electrically conductive filling layer
162
.
An insulation collar
168
is formed at an upper section or upper region of the trench. In this case, the insulation collar
168
prevents a leakage current from the contact diffusion region
125
to the buried plate
165
. Such a leakage current is undesirable, in particular, in memory circuits, because it reduces the charge retention time, or retention time, of a semiconductor memory cell.
In accordance with
FIG. 1
, the conventional semiconductor memory cell with trench capacitor furthermore has a buried well or layer
170
, the peak concentration of the dopants in the buried n-type well lying approximately in the lower end of the insulation collar
168
. The buried well or layer
170
substantially serves for connecting the buried plates
165
of a multiplicity of adjacent DRAM semiconductor memory cells or capacitors
160
in the carrier substrate
101
, which is preferably composed of silicon semiconductor material.
An activation of the selection transistor
110
by application of a suitable voltage to the gate
112
substantially enables access to the trench capacitor
160
, the gate
112
usually being connected to a word line
120
and the diffusion region
113
to a bit line
185
in the DRAM array. In this case, the bit line
185
is isolated from the diffusion region
113
by a dielectric insulation layer
189
and electrically connected through a contact
183
.
Furthermore, to isolate a respective semiconductor memory cell with associated trench capacitor from adjoining cells, a hallow trench isolation (STI)
180
is formed at the surface of the semiconductor substrate
101
. In accordance with
FIG. 1
, by way of example, the word line
120
can be formed above the trench and in a manner isolated by the shallow trench isolation (STI). As a result, so-called folded bit line architecture is obtained.
As such, a semiconductor memory cell is obtained that has a minimal space requirement and is, thus, optimally suited to large-scale integrated circuits.
What is disadvantageous, however, in the case of such a conventional semiconductor memory cell is that the insulation collar
168
is usually disposed only in the same height around the trench and, consequently, undesirable leakage currents into the semiconductor substrate
101
can still occur in a connection region AB.
In principle, the insulation collar
168
could also be raised in a stepped manner in its other regions to release only the connection diffusion region
125
, but additional and costly photolithographic steps and etching steps have to be employed. These steps are very complicated and cost-intensive, however, particularly in the case of large scale integrated circuits, on account of so-called overlay problems and “critical dimension” tolerances.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating self-aligning mask layers that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that permits fabrication of microelectronic and micromechanical systems simply and cost-effectively.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for fabricating a self-aligning mask layer, including the steps of (a) forming a surface to be masked in a carrier substrate, the surface having different radii of curvature, (b) forming an undensified conformal insulation layer on the surface to produce, due to the different radii of curvature, regions with different mechanical stress in the conformal insulation layer, and (c) etching to remove partial regions of the conformal insulation layer in a manner dependent on the different mechanical stress in the conformal insulation layer.
In particular, the invention provides a method for fabricating a self-aligning mask layer in which the above-described insulation collar is formed in a particularly simple and cost-effective manner so as to produce a reduced leakage current and improved charge retention properties.
In particular by virtue of forming a surface to be masked in a carrier substrate, the surface having different radii of curvature, and subsequently forming an undensified conformal insulation layer on the surface such that, on account of the different radii of curvature, regions with different mechanical stress are produced in the insulation layer, it is possible, in the course of an etching that is subsequently carried out, on account of an established etching rate dependence of partial regions of the insulation layer with different mechanical stress, to realize a sublithographic patterning, for example, for the formation of contact regions.
In accordance with another mode of the invention, step (a) is carried out by forming a trench in the carrier substrate. The surface to be masked constitutes a trench surface.
In accordance with a further mode of the invention, step (b) is carried out by forming, as the conformal insulation layer, at least one of undensified oxides and glasses based on silicon oxide.
Preferably, an undensified oxide and/or glasses based on silicon oxide, such as, for example, BPSG, PSG, and spin-on glasses, are formed as the conformal insulation layer. Such materials or layers exhibit a high dependence of their inner mechanical stress with regard to a surface structure to be masked. By the selection of respective radii of curvature on the surface to be masked, sublithographic structures can, thus, be realized particularly simply and

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