Method for fabricating self-aligned semiconductor devices utiliz

Details Method for fabricating self-aligned semiconductor devices utiliz Method for fabricating self-aligned semiconductor devices utiliz

1977-07-12

1979-01-23

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29571, 29576W, 29578, 148 15, 148175, 156643, 156652, 156653, 156657, 156662, 357 23, 357 40, 357 42, 357 50, 357 54, H01L 2122, H01L 21316

Patent

active

041359542

ABSTRACT:
A method for fabricating self-aligned regions of semiconductor devices such as bipolar or field effect transistors using three masking layers which are selectively etchable with respect to each other on the surface of the semiconductor body. A dimensional mask is deposited over the three layers so that the set of all of the self-aligned impurity regions to be formed through the surface of the body are defined by etching the upper masking layer, with the intermediate layer acting as an etch-stop. Using conventional wet or dry resist processes, each subset of similar impurity regions may then be formed selectively through the intermediate and lower layers without the need for precisely aligning any subsequent mask.

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Dhaka et al., "Masking Technique" I.B.M. Tech. Discl. Bull., vol. 11, No. 7, Dec. 1968, p. 864-865.

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