Fishing – trapping – and vermin destroying
Patent
1990-09-20
1991-10-29
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 28, 437 89, 437 91, 437162, 437909, 437112, 437924, 148DIG27, 148DIG29, 148DIG43, 148DIG124, H01L 2120, H01L 21331
Patent
active
050616447
ABSTRACT:
A method of forming a self-aligned contact to a transistor component located on a semiconductor substrate comprising forming a transistor component opening in a masking layer overlying a semiconductor substrate and using epitaxial lateral overgrowth to form a self-aligned contact, the epitaxial overgrowth beginning in the masking layer opening at an upper surface of the semiconductor substrate and extending normal to and laterally over the masking layer surface.
REFERENCES:
patent: 3746908 (1973-07-01), Engeler
patent: 4190949 (1980-03-01), Ikeda et al.
patent: 4269631 (1981-05-01), Anantha et al.
patent: 4507158 (1985-03-01), Kamins et al.
patent: 4508579 (1985-04-01), Goth et al.
patent: 4522662 (1985-06-01), Bradbury et al.
patent: 4551394 (1985-11-01), Betsch et al.
patent: 4566914 (1986-01-01), Hall
patent: 4578142 (1986-03-01), Corboy, Jr. et al.
patent: 4637127 (1987-01-01), Kurogi et al.
patent: 4651407 (1987-03-01), Bencuya
patent: 4716128 (1987-12-01), Schubert et al.
patent: 4829016 (1989-05-01), Neudeck
Liu Michael S. T.
Yue Jerry
Bruns Gregory A.
Gresens John J.
Hearn Brian E.
Honeywell Inc.
Nguyen Tuan
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