Method for fabricating self-aligned high resolution non planar d

Details Method for fabricating self-aligned high resolution non planar d Method for fabricating self-aligned high resolution non planar d

1979-04-09

1981-05-26

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29580, 148 15, 148187, H01L 21302

Patent

active

042689520

ABSTRACT:
A method is disclosed for fabricating structures having electrically conductive regions such as high resolution semiconductor device and circuit designs which require only low resolution alignment steps during fabrication. The method is used to fabricate metal semiconductor field effect transistors (MESFET) and metal oxide semiconductor field effect transistors (MOSFET) devices and incorporates the following features. A device with very small (i.e. submicron) dimensions is positioned in a relatively large device well such that the exact position of the device in its well is not critical. Isolation and interconnection of devices in different wells is achieved by standard masking and alignment techniques with a resolution corresponding to the larger dimensions of the device wells. All high resolution features of the device are contained in a single masking level, however, to separate and insulate different elements of the device at such small dimensions different height levels are used in the device so that one masking step can produce zero lateral spacing between the different device elements. The disclosure provides examples of the present method applied to the fabrication of a MESFET device and a MOSFET device and to the isolation and interconnection of single devices into large circuits on a semiconductor chip.

REFERENCES:
patent: 3518509 (1970-06-01), Cullis
patent: 3598664 (1971-08-01), Kilby
patent: 3968562 (1976-07-01), Van Lierof
patent: 4027380 (1977-06-01), Deal

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