Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
1999-01-14
2001-05-29
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000
Reexamination Certificate
active
06238932
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates, in general, to a method for preventing oxidation of a bottom electrode in a ferroelectric capacitor. More specifically, this invention relates to a process for forming a ferroelectric capacitor wherein a metal is deposited at a high temperature or annealed at a high temperature prior to deposition of a ferroelectric (e.g. PZT) layer.
BACKGROUND OF THE INVENTION
Without limiting the scope of the invention, its background is described in connection with use of an oxidation barrier in a capacitor having a ferroelectric dielectric such as lead zirconium titanate (PZT) or bismuth strontium titanate.
Many semiconductor makers are making efforts to develop ferroelectric non-volatile memory (FeRAM) because it has potential to replace current memory types (DRAM, SRAM, EEPROM, etc.) Ferroelectric memory also has many applications in digital signal processors and smart cards.
SUMMARY OF THE INVENTION
To achieve a high integration density of ferroelectric memory cells, the cell structure in
FIG. 1
has been proposed. Unfortunately, we have found that it has been difficult to form reliable ferroelectric capacitors because the ferroelectric dielectric needs to be formed in a highly-oxidizing atmosphere, but this causes oxidation of conductors below the capacitor by oxygen penetrating the bottom electrode metal layer.
The present invention involves a technique to prevent a barrier film from oxidizing which allows for the formation of a reliable ferroelectric (e.g. PZT) capacitor.
One use of this invention can be to provide a method for producing a ferroelectric capacitor with minimal oxidation occurring to conducting layers below the ferroelectric layer. This reduced oxidation will, e.g. reduce peeling of the bottom electrode.
The invention can involve a process for fabrication of a bottom electrode for a ferroelectric semiconductor, comprising the steps of depositing a bottom electrode over a conductive plug in an inert atmosphere at a temperature between 300 and 800 C, depositing a ferroelectric capacitor dielectric over the bottom electrode, and depositing a top electrode over the ferroelectric capacitor dielectric.
More specifically, one embodied process for fabrication of a bottom electrode for a ferroelectric semiconductor comprises the steps of depositing a titanium nitride layer over a conductive plug, the titanium nitride layer having a thickness between 10 and 100 nm, depositing a bottom electrode selected from the group consisting of iridium, platinum, ruthenium, and palladium over the titanium nitride layer in a vacuum at a temperature of about 500 C, the bottom electrode having a thickness of between 50 and 400 nm, depositing a ferroelectric capacitor dielectric over the metal, and depositing a top electrode over the ferroelectric capacitor dielectric.
REFERENCES:
patent: 5418388 (1995-05-01), Okudaira et al.
patent: 5874364 (1999-02-01), Nakabayashi et al.
patent: 6054331 (2000-04-01), Woo et al.
Aoki Katsuhiro
Fukuda Yukio
Sakoda Tomoyuki
Brady W. James
Hoel Carlton H.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tsai Jey
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