Metal fusion bonding – Process – Plural filler applying
Reexamination Certificate
2001-04-11
2003-10-14
Dunn, Tom (Department: 1725)
Metal fusion bonding
Process
Plural filler applying
C228S165000, C174S250000, C174S251000, C174S261000
Reexamination Certificate
active
06631838
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a printed circuit board, and more particularly to a method for fabricating a printed circuit board in which when a solder resist is coated, an air space is not allowed to remain in a blind via hole, thereby heightening the reliability of the attachment between the printed circuit board and a solder resist layer.
2. Description of the Background Art
FIG. 1
is a sectional view of a printed circuit board in accordance with a conventional art.
As shown in the drawing, a first conductive circuit pattern
3
a
is formed at the upper surface of a substrate
1
, and a first insulation resin layer
5
a
is formed at the upper surface of the first conductive circuit pattern
3
a
. Via holes
7
are formed at the first insulation resin layer
5
a
, through which the upper surface of the first conductive circuit pattern
3
a
is exposed.
A second conductive circuit pattern
3
b
is formed at the upper surface of the first insulation resin layer
5
a
, and a first plated layer
9
a
is formed at the upper surface of the second conductive circuit pattern
3
b
, at the inner wall face of the via hole
7
and at the upper surface of the first conductive circuit pattern
3
a
exposed through the via hole
7
. The second conductive circuit pattern
3
b
formed at the upper surface of the first insulation resin layer
5
a
and the first conductive circuit pattern
3
a
formed at the lower surface of the first insulation resin layer
5
a
are electrically connected.
A second insulation resin layer
5
b
is formed at the upper surface of the second plate layer
9
a
and at the upper surface of the first insulation resin layer
5
a.
Via holes
7
are formed at the upper surface of the second insulation resin layer
5
b
with the upper surface of the first plated layer
9
a
partially exposed.
A third conductive circuit pattern
3
c
is formed at the upper surface of the second insulation resin layer
5
b.
A second plated layer
9
b
is formed at the upper surface of the third conductive circuit pattern
3
c
, the inner wall of the via hole
7
and the first plate layer
9
a.
The second conductive circuit pattern
3
b
and the third conductive circuit pattern
3
c
are electrically connected by the second plated layer
9
b.
A solder resist
11
is coated at the upper surface of the second plated layer
9
b
and of the second insulation resin layer
5
b
. The exposed portion
12
of the second plated layer
9
b
which has not been coated with the solder resist
11
is connected with an outer lead of an electronic part.
The printed circuit board in the above described structure has the following problems.
In fabricating the printed circuit board, the following problems arise when the solder resist layer is finally coated at the upper surface of the plated layer. For example, the surface of the plated layer of the printed circuit board is rough, not level. In other words, the surface of the plated layer at the portion where the via holes are formed is concave compared with the other portion where a via hole is not formed. In the case where the solder resist layer is coated at the upper surface of the plated layer having a level portion and a collapsed portion, the solder resist does not entirely fill the collapsed portion, forming a void. The reason for this is that, when the solder resist is applied, the air in the via hole is not completely removed, whereby the air remaining in the via hole forms an air space. The air space prevents the solder resist from completely filling the via hole.
FIG. 2
illustrates a via hole
7
, a solder resist
11
and a void
20
formed in the via hole
7
. The same elements as in
FIG. 1
are given the same reference numerals. In addition, a plated layer
9
b
is formed at the surface of the inner wall at the bottom surface of the via hole
7
and at the upper surface of the conductive circuit pattern
3
c
. The air fills the void
20
within the via hole
7
, and the solder resist
11
covers the upper surface of the void
20
.
The void formed in the via hole
7
as shown in
FIG. 2
causes the following problems. When the printed circuit board is exposed to a high temperature process such as in the case where parts are mounted on the printed circuit board, the air present in the void
20
, results in a rupturing of the solder resist
11
which covers the void
20
. Then, the solder resist
11
falls out and the plated layer
9
b
and the conductive circuit pattern
3
c
also break down, degrading the reliability of the printed circuit board.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method for fabricating a reliable printed circuit board.
Another object of the present invention is to provide a method for fabricating a printed circuit board in which an air space does not result in a portion of a printed circuit board collapsing, thereby improving the adhesion reliability between the printed circuit board and a solder resist.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a method for fabricating a printed circuit board including the steps of: fabricating a printed circuit board having at least one collapsed portion; depositing a first solder resist in the collapsed portion; exposing the first solder resist-coated printed circuit board at a pressure lower than atmospheric pressure for a predetermined time; coating a second solder resist on the entire surface of the printed circuit board; and drying and hardening the first and the second solder resists.
To achieve the above objects, the method for fabricating a printed circuit board further comprises a step of mounting a window screen having a window larger than the collapsed portion at a position corresponding to the collapsed portion on the upper surface of the printed circuit board, before the step of coating the first solder resist.
To achieve the above objects, in the step of exposing the printed circuit board to a pressure lower than atmospheric pressure in the method for fabricating a printed circuit board, the pressure is about {fraction (1/10)} of atmospheric pressure.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
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Ahn Young-Cheol
Kim Nam-Jin
Kim Won-Jae
Birch & Stewart Kolasch & Birch, LLP
Dunn Tom
Edmondson L.
LG Electronics Inc.
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