Method for fabricating polycrystalline silicon having micro roug

Semiconductor device manufacturing: process – Making passive device – Stacked capacitor

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438964, H01L 21205

Patent

active

057233799

ABSTRACT:
A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective area and is suitable for a capacitor electrode because of its increased effective surface area.

REFERENCES:
patent: 4301588 (1981-11-01), Horng et al.
patent: 4441249 (1984-04-01), Alspector et al.
patent: 4742018 (1988-05-01), Kimura et al.
patent: 4757360 (1988-07-01), Faraone
patent: 4774202 (1988-09-01), Pan et al.
patent: 4874716 (1989-10-01), Rao
patent: 4905072 (1990-02-01), Komatsu et al.
patent: 4951175 (1990-08-01), Kurosawa et al.
patent: 5017505 (1991-05-01), Fujii et al.
patent: 5025741 (1991-06-01), Suwani et al.
patent: 5037773 (1991-08-01), Lee et al.
patent: 5061650 (1991-10-01), Dennison et al.
patent: 5064779 (1991-11-01), Hasegawa
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5102813 (1992-04-01), Kobayashi et al.
patent: 5110752 (1992-05-01), Lu
patent: 5114873 (1992-05-01), Kim et al.
patent: 5124767 (1992-06-01), Koyama
patent: 5183772 (1993-02-01), Jim et al.
patent: 5227651 (1993-07-01), Kim et al.
patent: 5245206 (1993-09-01), Chu et al.
patent: 5270224 (1993-12-01), Furumura et al.
patent: 5290729 (1994-03-01), Hayashide et al.
patent: 5302844 (1994-04-01), Mizuno et al.
patent: 5385863 (1995-01-01), Tatsumi et al.
Kobayashi et al, "Novel Highly Conductive Polycrystalline Silicon Films Reducing Processing Temperature Down to 650.degree. C. Conference on Solid State Devices and Materials", 1988, pp. 57-60.
Watanabe et al, A new stacked capacitor structure using hemispherical grain(HSU), polysilicon electrode, 22nd conference on solid state devices and materials, 1990 pp. 873-876.
T. Mine et al., "Capacitance-Enhanced Stacked-Capacitor With Engraved Storage Electrode for Deep Submicron DRAMs," Solid State Devices and Materials, Aug. 28-30, 1989, pp. 137-140.
H. Cerva et al., "Microstructure and Interfaces of Polysilicon in Integrated Circuits," Polycrystalline Semiconductors, Grain Boundaries and Interfaces, Proceedings of the International Symposium, Malente, West Germany, 29 Aug.-2 Sep. 1988, Springer Proceedings in Physics, vol. 35, pp. 354-365.
Hyung Sup Yoon et al., "Structure and Electrical Resisitivity of Low Pressure Chemical Vapor Deposited Silicon," J. Vac. Sci. Technol. A, vol. 4, No. 6, Dec. 1986, pp. 3095-3100.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for fabricating polycrystalline silicon having micro roug does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating polycrystalline silicon having micro roug, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating polycrystalline silicon having micro roug will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2247128

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.