Method for fabricating polycrystalline silicon having micro roug

Details Method for fabricating polycrystalline silicon having micro roug Method for fabricating polycrystalline silicon having micro roug

1991-03-19

1994-11-22

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437 60, 437919, 437967, 437977, H01L 21205

Patent

active

053669177

ABSTRACT:
A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable fur a capacitor electrode because of its increased effective surface area.

REFERENCES:
patent: 4905072 (1990-02-01), Komatsu et al.
patent: 4951175 (1990-08-01), Kurosawa et al.
Cerva et al., "Microstructure and Interfaces of Polysilicon in Integrated Circuits", Polycrystalline Semiconductors, Grain Boundaries and Interfaces, Proceedings of the International Symposium, Malente, West Germany, 29 Aug.-2 Sep. 1988, pp. 354-365.
Yoon et al., "Structure and Electrical Resistivity of Low Pressure Chemical Vapor Deposited Silicon", Journal of Vacuum Science & Technology A (Vacuum, Surfaces, and Silicon), vol. 4, No. 6, 1986, pp. 3095-3100.
Patent Abstracts of Japan, unexamined applications, E field, vol. 13, No. 344, Aug. 3, 1989, The Patent Office Japanese Government, p. 36 E 797, Kokai-No. 1-102 918 (NEC).
T. Mine et al., "Capacitance-Enhanced Stacked-Capacitor With Engraved Storage Electrode For Deep Submicron DRAMs," Solid State Devices and Materials, Aug. 28-30, 1989, pp. 137-140.

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