Etching a substrate: processes – Forming or treating optical article
Reexamination Certificate
2000-07-14
2003-08-12
Beck, Shrive P. (Department: 1763)
Etching a substrate: processes
Forming or treating optical article
C216S039000, C065S379000, C065S384000, C065S385000
Reexamination Certificate
active
06605228
ABSTRACT:
TECHNICAL FIELD
The present invention relates to planar optical waveguide devices, and in particular to a method for fabricating planar optical waveguide devices which are, not exclusively, suited for use in the field of optical communication.
BACKGROUND OF THE INVENTION
Planar optical waveguide devices have been conventionally Used in the field of optical communication in such forms as star couplers or signal splitters. Such an optical waveguide device is typically provided with an embedded waveguide structure based on a step-wise refractive index distribution.
Japanese patent laid open publications Nos. 61-210304 and 1-189614 disclose planar optical waveguide devices having an embedded structure. The various layers are formed either by CVD or deposition of glass powder followed by sintering (FHD: flame hydrolysis deposition). Japanese patent laid open publication No. 61-210304 proposes to form a recess in a substrate to form a core therein. To achieve a desired circular cross section, the recess having a rectangular cross section is fire polished so as to have a more circular cross section as illustrated in
FIG. 1
of this prior patent publication. Such a waveguide device can be fabricated as summarized in the following.
First of all, a substrate or a buffer layer serving as a lower clad layer is prepared, and a core layer is formed on the lower clad layer. The core layer is appropriately patterned into core segments of a desired configuration typically by reactive ion etching (RIE). Then, an upper clad layer is placed on both the core and the lower clad layer. The obtained assembly is then cut into a desired size and configuration, and the input and output ends of the assembly is polished into optical planes. These layers are typically made of SiO
2
, and a desired refractive index distribution can be achieved by adding suitable dopants to the appropriate layers.
A low-temperature film-forming process such as CVD, plasma CVD, PVD, and vacuum PVD is advantageous in controlling the thickness of each layer, and evenly distributing dopants in each layer. However, the upper clad layer may fail to fill the gaps between adjacent core segments or the material for the core may fail to fill the recess in the lower clad layer, and voids may develop in the upper clad layer or the core. Such voids are known to reduce the transmission efficiency of the device due to the scattering of the signal light, and are desired to be eliminated. When a recess is formed in the lower clad layer to form the core in the recess, the upper clad layer may be placed on a planar surface, and creation of voids in the upper clad layer can be avoided. However, voids tend to be produced in the core by the material of the core failing to fill the recess completely.
FHD involves a higher temperature, and allows the material to fill gaps or recesses more freely, in particular by properly selecting the softening point of the selected glass material. However, controlling the softening point requires addition of dopants which are also known to change the refractive index of the material. Therefore, it is difficult to adjust the amount and selection of dopants which would result in a desired softening point and refractive index at the same time. Oftentimes, a desired softening point may not be achieved, and voids may be created in the upper clad layer or the core. Also, an even distribution of dopants is difficult to achieve with FHD. Raising the temperature of the glass material may be beneficial in softening the glass material and evenly distributing the dopants, but may soften the already formed layer or may cause the dopants to migrate from one layer to another.
The inventors proposed the use of the hot isostatic pressing (HIP) process for removing voids that may be created in the upper clad layer in the copending patent application No. 9/175,137 filed Oct. 19, 1998. The contents of this copending patent application are hereby incorporated in this application by reference.
BRIEF SUMMARY OF THE INVENTION
In view of such problems of the prior art, a primary object of the present invention is to provide a method for fabricating planar optical waveguide devices which can eliminate voids that may develop in the core and/or upper clad layer of an optical waveguide device.
A second object of the present invention is to provide a method for fabricating planar optical waveguide devices which can minimize the possibility of defective products, and can thereby reduce the fabrication cost of each unit.
A third object of the present invention is to provide a method for fabricating planar optical waveguide devices which can fabricate durable devices through elimination of residual stresses in each layer of the device.
According to the present invention, such objects can be accomplished by providing a method for fabricating a planar optical waveguide device having a plurality of core segments formed between a lower clad layer and an upper clad layer, comprising the steps of: preparing a lower clad layer consisting of a glass substrate; forming a core layer on said lower clad layer; patterning said core layer into a plurality of core segments; forming an upper clad layer on said lower clad layer and said core segments, and conducting a hot isostatic pressing process on an assembly of said lower clad layer, core segments and upper clad layer at a temperature higher than 800° C. and a pressure higher than 1,000 kgf/cm
2
.
The lower clad layer may consist of a substrate or a buffer layer formed on a substrate. Each layer may be formed either by a low-temperature film-forming process or by the FHD process. The HIP process is also effective in eliminating voids when the core is formed in a recess of the lower clad layer. According to the tests conducted by the inventors, it was found that the HIP process can be conducted without requiring any protective layer or a gas barrier through proper selection of the condition for the HIP process, as opposed to the common belief that a protective layer or a gas barrier Is essential for the HIP process.
REFERENCES:
patent: 5858051 (1999-01-01), Komiyama et al.
patent: 6122934 (2000-09-01), Narita et al.
patent: 6205818 (2001-03-01), Seward, III
patent: 61-210304 (1986-09-01), None
patent: 1-189614 (1989-07-01), None
Patent Abstracts of Japan, Publication No. 08043653, Feb. 16, 1996.
Patent Abstracts of Japan, Publication No. 10197737, Jul. 31, 1998.
Patent Abstracts of Japan, Publication No. 11125727, May 11, 1999.
Kawaguchi Shigeru
Masuda Michiya
Natsume Yutaka
Senda Takayuki
Beck Shrive P.
MacPherson Kwok & Chen & Heid LLP
NHK Spring Co. Ltd.
Olsen Allan
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