Method for fabricating pillar bipolar transistor

Details Method for fabricating pillar bipolar transistor Method for fabricating pillar bipolar transistor

1995-06-06

1996-04-09

Fourson, George

Fishing, trapping, and vermin destroying

437 32, 437 33, 437 63, 437 67, 437 26, 257518, 257575, 257576, 257588, 148DIG10, 148DIG11, 1566331, H01L 21265

Patent

active

055061575

ABSTRACT:
Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterned insulating layer as a mask to form first and second pillarss separated by a trench therein; injecting an impurity using a mask to form a collector under the first and second pillars and in the second pillar; depositing a first oxide layer and a first polysilicon layer thereon; polishing the first polysilicon layer using the first oxide layer as a polishing stopper; removing a portion of the first polysilicon layer and a portion of the first oxide layer to define an extrinsic base; etching the oxide layer formed on both sides of the first pillar to a predetermined depth to define a connecting portion and forming a buried polysilicon therein to form the connecting portion; depositing a second oxide layer and a second polysilicon layer thereon; polishing the second polysilicon layer using the second oxide layer as a polishing stopper; removing only the second oxide layer formed upward the first pillar to expose a surface of the first pillar; injecting an impurity in the first pillar to form a base at a center portion thereof; injecting an impurity to form an emitter at an upper portion of the first pillar; depositing a third polysilicon layer on the emitter, the third polysilicon layer being formed wider than the emitter; and forming self-aligned contact holes to form electrodes through the contact holes.

REFERENCES:
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patent: 5061645 (1991-10-01), Nakazato et al.
patent: 5409845 (1995-04-01), Robinson et al.
Chai et al, "A New Self-Aligned Bipolar Transistor Using Vertical Nitride Mask", IEDM 85, IEEE publication No. CH2252-5/85/0000-0026 (1985).

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