Method for fabricating partial SOI substrate

Details Method for fabricating partial SOI substrate Method for fabricating partial SOI substrate

2011-04-19

2011-04-19

Smith, Matthew S (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C257S347000

Reexamination Certificate

active

07927965

ABSTRACT:
A method for fabricating a partial silicon-on-insulator (SOI) substrate is disclosed. The method for fabricating a partial silicon-on-insulator (SOI) substrate includes forming an insulation pattern over a first silicon layer, forming a second silicon layer over the substrate structure including the insulation pattern, etching the second silicon layer to form trenches, and forming device isolation regions filling the trenches.

REFERENCES:
patent: 2007/0259500 (2007-11-01), Cheng et al.
patent: 2008/0035998 (2008-02-01), Ramaswamy et al.
patent: 2009/0200635 (2009-08-01), Koldiaev
“A Novel Body Effect Reduction Technique to REcessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain: Application to Sub-50nm DRAM Cell” Jong-Man Park et al., IEEE, 2007, pp. 903-906.
Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Feb. 16, 2011.

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