Method for fabricating paired MOS transistors having a current-g

Details Method for fabricating paired MOS transistors having a current-g Method for fabricating paired MOS transistors having a current-g

1992-11-30

1994-12-06

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 29, 437 44, 437 52, 437 45, H01L 21265

Patent

active

053710266

ABSTRACT:
A semiconductor device (10) and process provides first and second, electrically coupled MOS transistors (14, 16) in which the current gain of the second MOS transistor (16) is greater than the current gain of the first MOS transistor (14). First and second gate structures (23, 25) are formed on a gate dielectric layer (26) overlying a semiconductor substrate (12). The gate dielectric layer (26) has a uniform thickness in all regions. The current gain differential between the first and second MOS transistors (14, 16) is obtained by selectively forming a dielectric intrusion layer (42) under the gate structure (23) of the first MOS transistor (14), whereas the dielectric layer (26) underlying the gate structure (25) of the second MOS transistor (16) retains the uniform thickness. The dielectric intrusion layer (42) causes a higher channel resistance in the first MOS transistor (14) which retards the current gain in the first MOS transistor (14) relative to the current gain of the second MOS transistor ( 16).

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Tseng, H., et al., "Advantages of CVD Stacked Gate Oxide For Robust 0.5 .mu.m Transistors" IEDM Technical Digest, 1991, pp. 75-78.
Ohkubo, H., et al., "16 Mbit SRAM Cell Technologies for 2.0 V Operation" IEDM Technical digest, 1991, pp. 481-484.
Pfiester, J., et al, "Poly-Gate Sidewall Oxidation Induced Submicrometer MOSFET Degradation" IEEE Electron Dev. Letters, (10), No. 8, Aug. 1989, pp. 367-369.

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