Method for fabricating multilayer insulator-semiconductor memory

Details Method for fabricating multilayer insulator-semiconductor memory Method for fabricating multilayer insulator-semiconductor memory

1975-08-18

1976-06-15

Weiffenbach, Cameron K.

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

357 24, 357 54, 427 85, 427126, 427255, H01L 1100, H01L 1500, B05D 512

Patent

active

039640850

ABSTRACT:
An SI.sub.1 I.sub.2 M (semiconductor-insulator.sub.1 -insulator.sub.2 -metal) memory structure, containing an impurity such as tungsten concentrated in a region including the interface ("I.sub.1 I.sub.2 ") region between the I.sub.1 and I.sub.2 region, is fabricated by depositing an oxide of the impurity, such as tungsten trioxide, on the then exposed, I.sub.1 layer prior to fabricating the I.sub.2 layer. The oxide of the impurity, such as tungsten trioxide, can be advantageously deposited by means of reactive evaporation.

REFERENCES:
patent: 3665423 (1972-05-01), Nakanuma
patent: 3877054 (1975-04-01), Boulin et al.
L. Holland, "Vacuum Deposition of Thin Films", Wiley & Sons, Inc., N.Y., 1956, pp. 122-125, 210-211, 448-453 and 482-483.
Per Kofstad, "High-Temperature Oxidation of Metals", Wiley & Sons, Inc., N.Y., 1966, pp. 251-261.

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