Method for fabricating multi-level interconnection structure for

Details Method for fabricating multi-level interconnection structure for Method for fabricating multi-level interconnection structure for

1993-12-10

1997-10-14

Fourson, George

Fishing, trapping, and vermin destroying

1566361, H01L 2144

Patent

active

056772394

ABSTRACT:
A method for fabricating a semiconductor device includes the steps of forming an interconnect metal film on an insulating layer and forming, on a surface of the interconnect metal film, a first insulating film formed of P--SiN. The first insulating film and the interconnect metal film are simultaneously patterned to form a lower interconnect. On the resulting surface, a second insulating film having a polishing rate higher than that of the first insulating film is formed. The entire surface of the second insulating film is flattened by a chemical mechanical polishing process using the first insulating film as a stopper. Then, on the resulting surface, a third insulating film is formed. According to one embodiment, the first insulating film used as the stopper remains on the lower interconnect but not between adjacent interconnects and, according to another embodiment, such film is completely removed by etching. Thus, an increase in the capacitance between the interconnects is prevented and any stress migration therein is suppressed.

REFERENCES:
patent: 4511429 (1985-04-01), Mizutani et al.
patent: 4839311 (1989-06-01), Riley et al.
patent: 5187121 (1993-02-01), Cote et al.
patent: 5272117 (1993-12-01), Roth et al.
patent: 5302551 (1994-04-01), Iranmesh et al.
patent: 5306665 (1994-04-01), Manabe
patent: 5382545 (1995-01-01), Hong

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