Method for fabricating multi-chip stacked package

Details Method for fabricating multi-chip stacked package Method for fabricating multi-chip stacked package

2011-04-05

2011-04-05

Vu, David (Department: 2829)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C257S686000, C257S676000, C257S777000, C257S696000, C257S723000, C438S123000

Reexamination Certificate

active

07919358

ABSTRACT:
A multi-chips stacked package method which includes providing a lead frame includes a top surface and a reverse surface formed by a plurality of inner leads and a plurality of outer leads; fixing a first chip on the reverse surface of the lead frame and the active surface of the first chip includes a plurality of first pads closed to the central region; forming a plurality of first metal wires, and the first pads are electrically connected to the first inner leads and the second inner leads by the first metal wires; forming a plurality of metal spacers on the thermal fin of the lead frame; fixing a second chip to electrically connect to the top surface of the first inner leads and the second inner leads; forming a plurality of second metal wires, and the second pads are electrically connected to the top surface of the first inner leads and the second inner leads; and flowing a molding to form an encapsulated material to cover the first chip, the first metal wires, the second chip, the second metal wires, the first inner leads and the second inner leads and the outer leads being exposed.

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U.S. Appl. No. 12/122,779, filed May 19, 2008, Shen, et al.

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