Method for fabricating MOS transistor having source/drain region

Details Method for fabricating MOS transistor having source/drain region Method for fabricating MOS transistor having source/drain region

1994-02-02

1997-03-04

Quach, T. N.

Fishing, trapping, and vermin destroying

437160, 437200, 437950, H01L 21225, H01L 21335

Patent

active

056078846

ABSTRACT:
A method for fabricating an MOS transistor having a source/drain region of shallow junction and a thin silicide film is disclosed. The present method takes advantage of the phase separation of the Ti-excessed titanium nitride film and is capable of forming a thin silicide film in a once metal thermal annealing process. The method employs dopant implant to the titanium nitride and silicide and thermal anneal for diffusion to form source and drain regions.

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Fujimura, N., et al., "TiSi.sub.2 Formation . . . ", Applied Surface Science 41/42 (1989), pp. 272-276.
Jing, H., et al., "Ultra Shallow Junction Formations . . . ", J. Electrochem. Soc., vol. 139, No. 1, Jan. 1992, pp. 196-218.
Paper Entitled "Ultra Shallow Junction Formation Using Diffusion From Silicides" By H. Jiang, et al., Published in J. Electrochem. Soc., vol. 139, No. 1, Jan. 1992. pp. 196-206.

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