Method for fabricating MOS device with reduced anti-punchthrough

Details Method for fabricating MOS device with reduced anti-punchthrough Method for fabricating MOS device with reduced anti-punchthrough

1995-01-10

1995-12-05

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 45, 437162, 257344, H01L 21336

Patent

active

054728975

ABSTRACT:
A method of fabricating MOS device with anti-punchthrough region is described. The area of anti-punchthrough region is reduced by using the control of double spacers. Moreover, this method utilizes the buried contact structure to connect to the source/drain regions, which not only reduces the contact resistance but also reduces the device size since the metal contact can be provided over the field oxide layer instead of the source/drain regions. Hence, this method is capable of fabricating submicron devices for semiconductor integrated circuit.

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