Method for fabricating MNOS memory circuits

Details Method for fabricating MNOS memory circuits Method for fabricating MNOS memory circuits

1977-04-07

1978-08-01

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

357 44, 357 91, H01L 21265

Patent

active

041040872

ABSTRACT:
MNOS memory circuit fabrication problems that result in leakage, memory device depletion mode switching and leakage paths at the edges of silicon islands are eliminated by a production process in which deposited and thermal oxides are used as a diffusion mask on the island edges, selective control of the threshold level of the memory device is achieved by ion implantation, and a thick oxide is grown on the silicon island edges to control charge injection.

REFERENCES:
patent: 3836894 (1974-09-01), Cricchi
patent: 3958266 (1976-05-01), Athanas
patent: 4002501 (1977-01-01), Tamura
P. J. Krick, "MNOS Memory Array on . . . Inendating Substrate", IBM Tech. Discl. Bull., 15 (1972) 466.
H. Runge, "Threshold Voltage Shift . . . by Ion Implantation", Electronic Engineering, Jan. 1976, p. 41.
M. R. MacPherson, "The Adjustment of MOS . . . Threshold . . . Ion Implantation", Appl. Phys. Lett., 18, (1971) 502.

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