Etching a substrate: processes – Gas phase and nongaseous phase etching on the same substrate
Reexamination Certificate
2000-06-19
2004-09-07
Goudreau, George A. (Department: 1763)
Etching a substrate: processes
Gas phase and nongaseous phase etching on the same substrate
C216S079000, C216S099000, C438S704000
Reexamination Certificate
active
06787052
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices, and more specifically to fabrication methods for deep (comparable to the thickness of the semiconductor wafer) etching that do not require expanded device surface areas when scaling up to larger diameter and thicker wafers.
2. Description of the Prior Art
Various kinds of semiconductor devices micro-sensors, micro-actuators and microstructures require fabricating deep cavities in the monocrystalline silicon substrates. For example, for integrated silicon pressure sensors the initial wafer may be locally etched from the back side through almost the entire thickness to form a thin silicon diaphragm. Similar deep etching (sometimes referred to as bulk micromachining) is used for other sensors and microstructures. For example, piezoresistive accelerometers, ink-jet print-heads, gas sensors, thermopiles, chemical sensors, silicon micro-valves, micro-relays, optical fiber aligners and others use deep silicon etching.
In the fabrication of piezoresistive accelerometers or print heads for ink-jet printers, the surface of an initial silicon wafer may have crystallographic orientation (
100
). During the fabrication process the wafer is etched locally from the backside to form a silicon diaphragm. Then for the print-head, the nozzles are etched in the diaphragm, or for the accelerometer the diaphragm is locally etched through to form the required shape of the suspension.
Prior art etching techniques often use wet anisotropic etching. As anisotropic wet etching is a batch process, the productivity is very high and cost is low compared to the other processes for silicon micromachining. FIGS.
1
(A)-(B) show a cavity
1
formed by wet anisotropic etching of a (
100
) silicon wafer
2
. The shape of the cavity
1
is determined by four {
111
} planes
3
. The etch rate of {
111
} planes
3
can be several hundred times less than the vertical etch rate of the wafer
2
. As a result, the position of the planes
3
remains substantially constant during etching and is determined by the layout of the etching mask and its orientation with respect to the crystallographic directions on the surface of the wafer. In many cases, the etched depth can be well controlled within 0.1-0.5 um with good uniformity across the wafer.
Low cost, high productivity, high accuracy, excellent uniformity and surface quality make wet anisotropic etching a desirable process for deep silicon micromachining. Among some disadvantages of anisotropic etching of (
100
) orientation silicon is the loss of real estate on the die and wafer surface. As indicated by FIGS.
1
(A)-(B), the {
111
} side walls
3
of the etched cavity
1
have about 54 degrees angle to the initial (
100
) surface of the wafer
2
. In order to receive, for example, a square diaphragm
4
with the side one mm, the size of the mask for deep etching to a depth H should be (1+H2)mm. A silicon wafer of four inches in diameter usually has a thickness of 0.4 mm. Therefore, the mask for 1 mm diaphragms and for deep (almost through) etching should be 1.56 mm. If the width of the frame around the cavity is 0.47 mm, then the total size of the die will be 2.5×2.5 mm and a four inch wafer will have about 1000 dies. Theoretically, transition to a six inch wafer should result in doubling the number of dies (of the same size) because the area is 2.25 times larger than the area of a four inch wafer. However, the thickness of a six 6 inch wafer is larger and usually equals at least 0.6 mm. Therefore, in order to fabricate the same one mm diaphragm, the mask should be 1.85 mm. With the same width of the frame the size of the die will be 2.79×2.79 mm instead of 2.5×2.5 mm, resulting in a loss of a minimum of 500 dies on each wafer.
Therefore, there is a need for a process of deep micromachining of silicon wafers which will allow about the same real estate for the mask at the surface of the wafer to form the cavities with different depths and the same size at the bottom (diaphragm). This would allow for decrease in the size of the die and its cost.
SUMMARY OF THE PRESENT INVENTION
An object of the present invention is to provide a method for decreasing the size and the cost of a die containing microstructures fabricated with deep anisotropic etching using at least a two-step micromachining of monocrystalline silicon wafers.
Another object of the present invention is to provide a method of fabricating cavities with the same size at the bottom (diaphragm) and with an opening mask, which is independent of the initial thickness of the silicon wafer.
Another object of the present invention is to provide a method of micromachining holes through the wafer with the opening mask, which is independent of the initial thickness of the silicon wafer.
Another object of the present invention is to provide a method of micromachining of monocrystalline silicon wafers, which allows fabricating microstructures inside the center of the die and local profiling of the outer surface of the die.
Another object of the present invention is to provide a method for micromachining of bar or grid-like microstructures, which provide additional mechanical strength of the die, and mechanical protection of microstructures inside the cavity, and the protective element and other elements (like diaphragm) can be fabricated within the same wafer and during the same process.
Another object of the present invention is to provide a method for micromachining of bar or grid-like microstructures, which after forming a cavity beneath their structures, can be used as a mask for local etching at the bottom of the cavity.
Another object of the present invention is to provide a method of fabricating channels and cavities completely inside a monocrystalline silicon wafer wherein these channels and cavities can be connected to the surface of the wafer in certain locations and can be used, for example, in microfluidics.
Another object of the present invention is to provide a method of fabricating sealed cavities or channels inside a monocrystalline silicon wafer, for example, for use as for absolute pressure sensors.
A preferred embodiment of the silicon wafer micromachining of the present invention comprises a combination of other than anistropic deep etching of silicon wafers followed by deep anisotropic etching. The additional etching or deposition of different materials allows fabricating various microstructures for numerous applications.
REFERENCES:
patent: 5857885 (1999-01-01), Laou et al.
patent: 6043135 (2000-03-01), Noda
patent: 2002/0094665 (2002-07-01), Villa et al.
patent: 4037202 (1992-05-01), None
Goudreau George A.
Law Offices of Thomas E. Schatzel A Prof. Corp.
Schatzel Thomas E.
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