Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Having enclosed cavity
Reexamination Certificate
2003-06-25
2004-11-30
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Having enclosed cavity
Reexamination Certificate
active
06825098
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention is in the field of semiconductor technology and relates to a method for fabricating microstructures.
Advancing scaling of integrated circuits and the associated miniaturization and increasing complexity of the structures contained in the integrated circuits entail a multiplicity of problems.
Thus, by way of example, the interconnect resistances of the individual interconnects within the wiring planes increase. The capacitive coupling between the interconnects increases at the same time. Associated with this is an unfavorable rise in the RC time constants, which lead to rising signal propagation times, decreasing limiting frequencies, high power loss densities and crosstalk effects. The technical literature also groups these problems under the term “wiring crisis”. In this respect, see, in particular, the technical articles by M. T. Bohr, “Interconnect Scaling—The Real Limiter to High Performance ULSI”,
IEDM
95, pages 241-244; S. Oh and K. Chang, “2001 Needs for Multi-Level Interconnect Technology”,
Circuits
&
Devices
, January 1995, pages 16-20; T. H. Ning, “0.1 &mgr;m Technology and BEOL”,
Mat. Res. Soc. Symp. Proc
., Vol. 427, 1996, pages 17-21; and K. Yamashita & S. Odanaka, “Interconnect Scaling Scenario using a Chip Level Interconnect Model”,
Symp. On VLSI Technology Digest of Technical Papers,
1997, pages 53-54.
A further problem associated with miniaturization can be examined in the proximity effects of lithography (e.g. U.S. Pat. No. 5,821,014, whose disclosure is incorporated herein by reference thereto) and etching technology. In the fabrication of integrated circuits, these effects lead to structural results which deviate from the desired structures prescribed on the lithography mask. In order to reduce or eliminate the proximity effects, it is necessary to resort to corrections (for example layout changes, U.S. Pat. No. 6,083,275, whose disclosure is incorporated herein by reference thereto) of ever increasing complexity. The effects discussed are based on the fact that individual process steps of the overall patterning process (exposure, development, plasma etchings, chemical mechanical polishing, etc.) depend on the local structural characteristic features (packing density, distances from adjacent structures, center and edge positions). The required layout changes have to be determined for each new layout, with a high outlay, and taken into account by means of suitable measures on the corresponding masks.
In order to reduce the RC time constants, use is often made of interconnects having high conductivity (e.g. copper) and dielectrics having low dielectric constants ∈
r
(often also designated by k). Diverse organic dielectrics having dielectric constants of approximately 2:5 are used as “low-k dielectrics” (e.g. so-called aerogels or xerogels, U.S. Pat. No. 6,277,728, whose disclosure is incorporated herein by reference thereto), but they are usually associated with diverse disadvantages (low thermal and chemical stability, hygroscopy, low blocking effect against the diffusion of e.g. copper, need to develop new deposition and patterning processes, new process installations). Porous inorganic dielectrics having even lower dielectric constants (e.g. porous SiON) are not yet ready for production at the present time.
The best material with extremely low ∈
r
is a vacuum or air (∈
r
=1). Therefore, a series of documents deal with techniques enabling the production of cavities between interconnects.
Thus, in accordance with U.S. Pat. No. 6,252,290 B1, whose disclosure is incorporated herein by reference thereto, by way of example, after the completion of the interconnects, cavities are produced between the interconnects by subsequent removal of insulation material.
U.S. Pat. No. 5,936,295, whose disclosure is incorporated herein by reference thereto, by contrast, exploits the porosity of a dielectric layer. After the completion of interconnect sections between which an auxiliary material is situated, the dielectric layer is applied to the interconnect sections and the auxiliary material. On account of the porosity of the dielectric layer, an etching substance can penetrate as far as the auxiliary material and remove the latter. As a result, cavities remain between the interconnect sections.
A similar approach is pursued by U.S. Pat. No. 6,297,125 B1, whose disclosure is incorporated herein by reference thereto, but here a dielectric covering layer with subsequently introduced slots is used, through which the etching substance can penetrate as far as the auxiliary material.
In contrast thereto, in accordance with U.S. Pat. No. 5,869,880, whose disclosure is incorporated herein by reference thereto, in each patterning plane (metallization and contact hole plane), the initially solid dielectric between the metal structures is finally patterned, thereby forming comparatively small openings in the dielectric in comparison with the metal structures, which openings contribute to a reduction of the dielectric constants taking effect.
An additional method for forming cavities between metal structures is disclosed in United States Patent Application Publication No. US 2001/0002732A1, whose disclosure is incorporated herein by reference thereto and which claims priority from DE 199 57 302 A1, wherein the cavities can be produced in a self-aligned manner with respect to the metal structures.
The above-mentioned methods have the disadvantage of a relatively high process complexity. Despite the cavities, capacitive couplings occur between the interconnects of different metallization planes on account of the dielectric layers (e.g. silicon oxide or silicon nitride) situated there. One possibility of reducing these capacitive couplings is afforded by the production of macroscopic cavity arrangements in these dielectric layers, i.e. in the contact hole plane, as is described for example in the German patent application DE 101 09 778.6 from the same applicant and in previously-cited U.S. Pat. No. 5,869,880.
However, the fundamental problems going back to the proximity effects of lithography and etching technology are not avoided with the abovementioned methods.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to specify a method in which the effects of proximity effects are considerably reduced.
This object is achieved by means of a method for fabricating microstructures comprises the following steps:
a) forming of a regular arrangement of closed cavities in a patterning layer arranged on a substrate, the cavities being separated from one another by partitions;
b) opening of selected cavities in which microstructures are intended to be produced;
c) removal of at least a portion of the partitions situated between adjacent opened cavities in order to form trenches extending over at least two cavities; and
d) introduction of a material into the trenches in order to fabricate the microstructures.
Accordingly, in accordance with the invention, firstly a regular arrangement of closed cavities is formed in a patterning layer. Regular structures can be fabricated with particularly high precision and accuracy in conjunction with a comparatively small extent. On account of the regularity, no local differences occur during the exposure and the etching. Therefore, local proximity effects are avoided particularly during a global regular patterning of the patterning layer. On the other hand, the regularity of the cavities also allows the imaging of cavities which are so small that they can no longer be imaged satisfactorily in the case of separate imaging. The individual cavities are separated from one another by partitions comprising the material of the patterning layer.
In order to reliably ensure the regularity, the closed cavities are formed by microelectronic processes known per se (e.g. CVD, lithography, etching, CMP). It is preferably the case, therefore, that in order to form the cavities, depressions are produced in the patterning layer and are closed with a covering layer, thereby producin
Gabric Zvonimir
Pamler Werner
Schwarzl Siegfried
Nhu David
Schiff & Hardin LLP
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