Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
2000-07-13
2001-11-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
C438S625000, C438S642000, C438S648000, C438S650000, C438S652000, C438S656000, C438S669000, C438S674000, C438S678000, C438S685000, C438S686000, C438S687000, C438S688000
Reexamination Certificate
active
06319741
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating metal interconnections used for flat panel displays such as liquid crystal displays (LCD), plasma display panels (PDP), electrochromic displays (ECD) and electroluminescent displays (ELD), as well as for printed wiring boards using ceramic substrates, or in other various fields.
In a flat panel display typified by LCDs, normally, display material such as liquid crystals or discharge gas is sandwiched between a pair of substrates, and a voltage is applied to the display material. In this case, metal interconnection lines made of electrically conductive material are arrayed on at least one of the substrates.
For example, in the case of an active matrix drive type LCD, gate electrodes and data electrodes are disposed in a matrix shape on one substrate (active matrix substrate), which is one of the pair of substrates between which the display material is sandwiched and held. A thin film transistor (TFT) and a pixel electrode are provided at each intersection of those electrodes. Generally, these gate electrodes and data electrodes are made of metal material such as Ta, Al or Mo, and deposited by a dry deposition technique such as vapor deposition, sputtering, or Chemical Vapor Deposition (CVD) process.
When making an attempt to obtain such flat panel displays having a larger area and/or a fine structure, the drive frequency is increased and thereby the resistance of metal interconnections and the parasitic capacitance increase. As a result of this, delay of driving signals comes up as a significant drawback.
Thus, in order to dissolve the delay of driving signals, there has been made an attempt to use Cu having lower electrical resistance (bulk resistivity: 1.7 &mgr;&OHgr;·cm) as the interconnection material, instead of Al (bulk resistivity: 2.7 &mgr;&OHgr;·cm), &agr;-Ta (bulk resistivity: 13.1 &mgr;&OHgr;·cm) or Mo (bulk resistivity: 5.8 &mgr;&OHgr;·cm), which are conventional interconnection materials. As a method for fabricating such metal interconnections, for example, the following (1) and (2) are available:
(1) “Low Resistance Copper Address Line for TFT-LCD” (Japan Display '89, pp. 498-501) discloses discussion results on a TFT-LCD in which Cu is used as the gate electrode material. According to this literature, it is expressly described that because a Cu film (low-resistance metal film) deposited by sputtering process with the aim of lowering the resistance has poor adhesion to the ground glass substrate, a ground metal film such as a metal film of Ta or the like deposited by sputtering process needs to be interveniently provided between the Cu film and the ground glass substrate in order to enhance the adhesion.
(2) Japanese Patent Laid-Open Publication HEI 2-83533 discloses a method of forming the metal interconnections of Cu by using a plating deposition technique without using any dry deposition technique such as sputtering process. In this case, to solve the poor adhesion of Cu film (low-resistance metal film) to the ground oxide (ITO), this method adopts metal interconnections of a Cu/Au/Ni layered structure in which a Ni film (ground metal film) and a Au film (anti-corrosion metal film) deposited. by electroless plating are interveniently provided between the Cu film and the ground oxide.
However, the metal interconnections shown above have the following drawbacks.
In the prior art example (1), in the process of forming a Cu film and a Ta film or the like by a dry deposition technique such as sputtering process for the formation of a Cu/Ta layered film, dry deposition process and etching process are necessary for the Cu film and the Ta film or the like, separately. This causes the number of processes to increase, which leads to a disadvantage of cost increase.
In the prior art example (2), the process of forming a Cu/Au/Ni layered film by plating deposition techniques needs to use electroless plating process for the Ni film. This is because when a metal is plated on an insulating substrate of glass or on an oxide film, a metal film is deposited generally by using electroless plating after a catalyst such as Pd is stuck on the insulating substrate or the oxide film. However, in the presence of a catalyst concentrated portion, i.e., in a poor dispersion of catalyst, there would occur abnormal growth of the Ni film at places where the poor dispersion of catalyst is present. This would inadversely cause minute protrusions on the surface of the deposited Ni film.
FIG. 4
is a schematic sectional view of a Ni film
102
formed by electroless plating on a surface of a glass substrate
101
on which Pd catalyst has been provided.
FIG. 4
shows that part of the columnar-grown Ni film
102
, where the Pd catalyst is concentrated, is abnormally grown to form a protrusion
103
. Such a protrusion failure shown in
FIG. 4
is often seen in the process of electroless plating, which is attributed to an effect of the particle size or dispersibility of the Pd catalyst.
Also, in normal plating techniques, even depending on differences in composition, pH, temperature, etc. of the plating bath, the resulting Ni film varies in crystallinity or deposition state. In some cases, the Ni film results in quite a meager state or a sparse state. In such a case, pinholes are prone to occur in the Ni film. When such a poor-quality Ni film is used as the ground, the Cu/Au film stacked on the Ni film is more prone to occurrence of local film floats, so-called “swelling” failures, corresponding to the pinholes of the Ni film.
On this account, in order to avoid adverse effects of film quality failures of pinholes or the like of the Ni film on the upper-layer Cu/Au film, the prior art example (2) describes a method of forming the Ni film of 0.4 &mgr;m or more in thickness, the Au film of 0.1 &mgr;m or more, and the Cu film of 0.8 &mgr;m or more. As a result of this, the total film thickness of metal interconnections composed of the Cu/Au/Ni layered film is 1 &mgr;m or more inevitably. However, because the prior art example (2) was based on the presumption that the metal interconnections are used in peripheral terminal part of a liquid crystal panel, the increase in the film thickness of the metal interconnections was not considered as an issue.
When the metal interconnections are applied not only to peripheral terminal part of the liquid crystal panel but also to bus lines (scan lines and signal lines) within the display area or the like, the increase in film thickness of metal interconnections causes the following drawbacks:
Firstly, in the case of a device structure in which other metal interconnections or thin films are formed on the above metal interconnections, there is a drawback that the other metal interconnections or the thin films cannot fully cover a step gap corresponding to the film thickness of the metal interconnections, i.e., a step gap between the insulating substrate and the metal interconnections, so that disconnections of the other metal interconnections or breaks of the thin films are more prone to occur.
Secondly, when the metal interconnections are used as bus lines within the display area of the liquid crystal panel, there is a drawback that the step gap corresponding to the film thickness of the metal interconnections, i.e., the step gap between the insulating substrate and the metal interconnections is so large that there is a higher probability of occurrence of orientation disturbance of liquid crystal molecules.
Accordingly, in order to use the metal interconnections in a wider variety of applications, the total film thickness of metal interconnections formed of the Cu/Au/Ni layered film is preferably as thin as possible, and more specifically, desired to be designed as not more than 0.5 &mgr;m. For implementation of such metal interconnections, it is indispensable to reduce the thickness of the ground Ni film, and improvement in the film quality of the Ni film is strongly demanded.
Therefore, an object of the present invention is to provide a method for fabricating metal interconne
Chikama Yoshimasa
Izumi Yoshihiro
Conlin David G.
Dike Bronstein Roberts & Cushman IP Group
Niebling John F.
Sharp Kabushiki Kaisha
Tucker David A.
LandOfFree
Method for fabricating metal interconnections and wiring... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating metal interconnections and wiring..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating metal interconnections and wiring... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2613171