Method for fabricating memory cell matrix having parallel source

Details Method for fabricating memory cell matrix having parallel source Method for fabricating memory cell matrix having parallel source

1991-07-23

1994-01-18

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 49, 437 43, H01L 21265

Patent

active

052799824

ABSTRACT:
A cell array for EPROM or ROM type memories has drain and source interconnection metal lines connecting in common drain and source regions, respectively, of the cells arranged on a same row of the array formed directly on the semiconductor substrate, superimposed at crossings to uninterrupted isolation strips formed on the semiconductor substrate for separating cells belonging to two adjacent columns of the array, and gate interconnection lines (WORD LINES), connecting the control gate electrodes of cells arranged on a same column, which run parallel to and between said isolation strips and superimposed at crossings to said underlying source and drain lines (BIT LINES). The array is markedly more compact than an array made according to the prior art though utilizing fabrication apparatuses with similar optical resolution, while maximizing the source and drain contact areas of the cells. In ROM devices, the customizing may advantageously take place during the final steps of the fabrication process by means of a gate contact mask having a reduced criticality in respect to a comparable drain contact mask used in prior art processes. The fabrication process employs self-alignment techniques and masks with a relatively low alignment criticality.

REFERENCES:
patent: 4271421 (1981-06-01), McElroy
patent: 4597060 (1986-06-01), Mitchell et al.
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 4957881 (1990-09-01), Crotti
patent: 5120571 (1992-06-01), Gill et al.
Kuniyoshi Yoshikawa et al., "An Asymmetrical Lightly Doped Source Cell for Virtual Ground High-Density EPROM's," IEEE Transactions on Electron Devices 37(4): 1046-51, Apr. 1990.

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