Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2006-11-02
2008-09-23
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C257SE21683
Reexamination Certificate
active
07427552
ABSTRACT:
A method for fabricating integrated circuit devices, e.g., Flash memory devices, embedded Flash memory devices. The method includes providing a semiconductor substrate, e.g., silicon, silicon on insulator, epitaxial silicon. In a specific embodiment, the semiconductor substrate has a peripheral region and a cell region. The method includes forming a first dielectric layer (e.g., silicon dioxide) having a first thickness overlying a cell region and a second dielectric layer (e.g., silicon dixode) having a second thickness overlying the peripheral region. In a specific embodiment, the cell region is for Flash memory devices and/or other like structures. The method forms a pad oxide layer overlying the first dielectric layer and forms a nitride layer overlying the pad oxide layer. The method includes patterning at least the nitride layer to expose a first trench region in the peripheral region and to expose a second trench region in the cell region, while a portion of the first dielectric layer having the first thickness in the cell region is maintained. The method includes forming a first trench structure having a first depth in the first trench region, while the portion of the first dielectric layer having the first thickness in the cell region protects the second trench region. The method includes removing the portion of the first dielectric layer to expose the second trench region. In a specific embodiment, the method includes subjecting the first trench region, including the first trench structure, and the second trench region with an etching process to continue to form the first trench structure from the first depth to a second depth and to form a second trench structure having a third depth within the second trench region. In the third depth is less than the second depth.
REFERENCES:
patent: 6995095 (2006-02-01), Yu
patent: 7211498 (2007-05-01), Kim
patent: 2002/0045303 (2002-04-01), Lee
patent: 2007/0001214 (2007-01-01), Park
Jin Da
Tang Shu Shu
Yang Zuo Ya
Ahmadi Mohsen
Geyer Scott B.
Semiconductor Manufacturing International (Shanghai) Corporation
Townsend and Townsend / and Crew LLP
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