Fishing – trapping – and vermin destroying
Patent
1995-07-18
1997-03-18
Fourson, George
Fishing, trapping, and vermin destroying
437 70, H01L 2176
Patent
active
056122470
ABSTRACT:
The method for fabricating a semiconductor device comprising the steps of: forming a first oxide film 12 on a surface of a semiconductor substrate 10 and forming a first nitride film 14 on a surface of the first oxide film 12, the first nitride film 14 having a predetermined pattern; isotropically etching the first oxide film 12, with the first nitride film 14 as a mask, to partially expose the surface of the semiconductor substrate 10 and form a hollow 16 just under an end portion of the first nitride film 14; forming a second oxide film 18, thinner than the first oxide film 12, at least on the surface of the semiconductor substrate 10 exposed at the outside of the first nitride film 14 and on a inner surface of the hollow 16; depositing a second silicon nitride film 20 on at least the second oxide film 18, the second silicon nitride film 20 being more liable to oxidation than the first silicon nitride film 14; and oxidizing a region where the first silicon nitride film 14 is absent, with the first silicon nitride film 14 as a mask, to form a device isolation film 24. The second silicon nitride film 20 is formed of a silicon nitride film which is more liable to oxidation, so that when the device isolation film 24 is formed by oxidizing away the second silicon nitride film 20, thickness disuniformity can be decreased.
REFERENCES:
patent: 4564394 (1986-01-01), Bussman
patent: 5118641 (1992-06-01), Roberts
patent: 5254494 (1993-10-01), van der Plas et al.
patent: 5358893 (1994-10-01), Yang et al.
patent: 5422300 (1995-06-01), Pfiester et al.
patent: 5453397 (1995-09-01), Ema et al.
J. R. Pfiester et al, "Nitride-Clad LOCOS Isolation for 0.25 .mu.m CMOS", 1993 Symposium on VLSI Technology digest of technical papers, pp. 139-140.
Fourson George
Fujitsu Limited
LandOfFree
Method for fabricating isolation region for a semiconductor devi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating isolation region for a semiconductor devi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating isolation region for a semiconductor devi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1705907