Method for fabricating isolation layer in semiconductor device

Details Method for fabricating isolation layer in semiconductor device Method for fabricating isolation layer in semiconductor device

2007-12-18

2009-08-18

Richards, N Drew (Department: 2895)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S425000, C438S427000, C438S435000, C438S444000, C438S622000, C438S623000, C438S633000, C257SE21546

Reexamination Certificate

active

07575981

ABSTRACT:
A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer, forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer, and forming a high density plasma (HDP) oxide layer for filling the remaining a portion of the trench.

REFERENCES:
patent: 6596607 (2003-07-01), Ahn
patent: 2002-0071169 (2002-09-01), None
patent: 2004-0110794 (2004-12-01), None
patent: 2006-0005504 (2006-01-01), None

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