Fishing – trapping – and vermin destroying
Patent
1995-09-08
1998-11-03
Fourson, George
Fishing, trapping, and vermin destroying
437 49, 437 48, H01L 2144, H01L 2176, H01L 218246
Patent
active
058307729
ABSTRACT:
Although the spacers are formed on the sidewalls of gate electrode and words lines via the same steps of deposition and etch-back processes, only the spacers disposed at the sidewalls of the gate electrode are practical for fabricating peripheral devices with LDD structure, and such fabrication is impractical in the memory cell region. On the contrary, the region beneath the spacers disposed at the sidewalls of word lines will become the path through which leakage current flows. The present invention makes use a shielding layer to cover the second active region as a masking, and then removes the spacers disposed at the sidewalls of word lines. Afterwards, isolating regions are formed through one implantation procedure to thereby decrease leakage current and simplify the process flow.
REFERENCES:
patent: 4574465 (1986-03-01), Rao
patent: 4922816 (1990-05-01), Ino
patent: 4977079 (1990-12-01), Kotaki
patent: 5158902 (1992-10-01), Hanada
patent: 5334543 (1994-08-01), Lin et al.
patent: 5418176 (1995-05-01), Yang et al.
patent: 5427966 (1995-06-01), Komorz
patent: 5449634 (1995-09-01), Inoue
patent: 5475036 (1995-12-01), Hong
patent: 5514611 (1996-05-01), Kim et al.
Chuang Yu-Chih
Kung Cheng-Chih
Tseng Che-Pin
Yeh Nai-Jen
Fourson George
United MicroelectronicsCorp.
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