Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2011-05-10
2011-05-10
Lindsay, Jr., Walter L (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S597000, C257SE21251
Reexamination Certificate
active
07939421
ABSTRACT:
A method for fabricating an integrated circuit structure includes the steps of forming a second dielectric layer on a substrate including a first conductive layer and a first dielectric layer, forming the second dielectric layer on the first conductive layer and the first dielectric layer, forming a hole exposing the first conductive layer in the second dielectric layer, forming a barrier layer inside the hole, and forming a second conductive layer on the barrier layer. In one embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal layer. In another embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal nitride layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal and metal nitride layer.
REFERENCES:
patent: 6444542 (2002-09-01), Moise et al.
patent: 2005/0124113 (2005-06-01), Yoneda
patent: 2007/0269918 (2007-11-01), Cho et al.
patent: 2008/0026597 (2008-01-01), Munro et al.
patent: 2008/0254314 (2008-10-01), Russell et al.
patent: 2008/0263855 (2008-10-01), Li et al.
patent: 2009/0017596 (2009-01-01), Hanson et al.
patent: 2009/0040805 (2009-02-01), Park et al.
patent: 2010/0006976 (2010-01-01), Kume et al.
patent: 2004-119754 (2004-04-01), None
patent: 2008-091835 (2008-04-01), None
Hamre Schumann Mueller & Larson P.C.
Lindsay, Jr. Walter L
Nanya Technology Corp.
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