Semiconductor device manufacturing: process – Chemical etching – Altering etchability of substrate region by compositional or...
Reexamination Certificate
1999-09-07
2001-07-03
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Altering etchability of substrate region by compositional or...
C438S745000, C438S756000
Reexamination Certificate
active
06255219
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to the fabrication of submicron semiconductor devices.
BACKGROUND OF THE INVENTION
Semiconductor devices include deep-submicron metal-oxide semiconductor fieldeffect transistors (MOSFET).
FIG. 1
illustrates a conventional cell of a MOSFET. The cell
100
comprises a gate
102
on a substrate
104
. The gate typically comprises a polysilicon layer
106
with a salicide layer
108
on top. Sidewall spacers
110
comprising oxide protect the gate
106
. The cell
100
also comprises a salicide layer
112
and a silicon nitride layer
114
on the substrate
104
next to the spacers
110
. In the substrate
104
on the source and drain sides are extensions
116
, halo implanted areas
118
, and the source
120
and drain
122
regions. The cell
100
has a lateral symmetric channel doping profile. However, as device dimensions are scaled down to the sub-100 nm regime, the speed of the device is not scaled in the same manner.
Accordingly, there exists a need for a method of fabrication of a submicron MOSFET which improves the speed of the device. The present invention addresses this need.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a submicron metal-oxide semiconductor field-effect transistor (MOSFET). The method includes providing a gate on a substrate, the substrate having a source side and a drain side, the drain side having a spacer area; forming a spacer at the spacer area; and performing a halo implant at the source side and the drain side, wherein the spacer prevents implantation in the spacer area, wherein the spacer facilitates formation of a lateral asymmetric channel. In the preferred embodiment, the spacer is formed by depositing an oxide layer on the gate and substrate, and then avoiding nitrogen implantation of the oxide layer in the spacer area while implanting nitrogen in the remainder of the oxide layer. The difference in the etch rates of oxide implanted with nitrogen and oxide not implanted with nitrogen allows for a selective etch of the oxide layer, resulting in the spacer in the spacer area. A lateral asymmetric channel is thus formed, and the speed of the submicron MOSFET is increased.
REFERENCES:
patent: 6043157 (2000-03-01), Gardner et al.
patent: 6083846 (2000-07-01), Fulford et al.
patent: 6107211 (2000-08-01), Tseng
“A High Performance 0.1 &mgr;m MOSFET with Asymmetric Channel Profile,” Akira Hiroki, Shinji Odanaka, and Atsushi Hori,IEEE 1995.
Long Wei
Xiang Qi
Advanced Micro Devices , Inc.
Powell William
Sawyer Law Group LLP
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