Method for fabricating high aspect ratio low resistivity lines/v

Details Method for fabricating high aspect ratio low resistivity lines/v Method for fabricating high aspect ratio low resistivity lines/v

1997-09-30

1999-03-02

Quach, T. N.

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Compound semiconductor

438648, 438658, 438660, 438687, 438688, H01L 2128

Patent

active

058770844

ABSTRACT:
A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6, can be used to produce an in-situ hard cap of W.sub.x Ge.sub.y. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.

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