Method for fabricating heterojunction bipolar transistors

Details Method for fabricating heterojunction bipolar transistors Method for fabricating heterojunction bipolar transistors

2001-03-30

2003-12-09

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C438S312000, C438S317000

Reexamination Certificate

active

06660607

ABSTRACT:

BACKGROUND
The present invention relates generally to semiconductor devices and, more particularly, to heterojunction bipolar transistors and methods of manufacturing the same.
With advances in high-speed communications and digital signal processing, there is a corresponding need for improved bipolar transistor characteristics. For example, in order to obtain the highest possible unity-gain cutoff frequency, the base region of the transistor should be as thin as possible. On the other hand, the highest possible frequency of oscillation is achieved when the base resistance is as small as possible. For a bipolar transistor, these requirements are at odds with one another because the base resistance thereof increases as its thickness decreases.
Silicon-germanium (SiGe) heterojunction bipolar transistors (HBT) provide significant leverage in the fabrication of npn transistors with low intrinsic base resistance. This is largely due to the fact that the base doping in an HBT transistor (e.g., with boron) can be increased without degrading the emitter injection efficiency. Furthermore, boron diffusion in SiGe is lower than in silicon, thereby resulting in transistors that are highly doped but with thin basewidths. However, existing HBT fabrication technology does present certain process integration problems. For instance, a low temperature epitaxial Si/SiGe layer is typically the first layer grown after an active area is defined for a transistor. Once formed, the Si/Ge layer is subsequently subjected to multiple thermal cycles and dopant implantation during the formation steps of the remaining elements of the transistor such as the deposition of oxide layers, nitride layers and the emitter. As a result, a doped base layer (e.g., with boron) is subjected to unnecessary diffusion which may ultimately cause an increased basewidth, even if the as-grown base layer is thin.
BRIEF SUMMARY
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for fabricating a heterojunction bipolar transistor having collector, base and emitter regions. In an exemplary embodiment of the invention, the method includes forming a silicon epitaxial layer upon a substrate, the silicon epitaxial layer defining the collector region. An oxide stack is formed upon the silicon epitaxial layer and a nitride layer is then formed upon the oxide stack. Next, an emitter opening is defined within the nitride layer before a base cavity is formed within the oxide stack. The base cavity extends laterally beyond the width of the emitter opening. A silicon-germanium epitaxial layer is grown within the base cavity, the silicon-germanium epitaxial layer defining the base region. Finally, a polysilicon layer is deposited upon said silicon-germanium epitaxial layer, the polysilicon layer defining the emitter region.
In a preferred embodiment, the base cavity is formed after the oxide stack and the nitride layer have been formed. In addition, a collector dopant material is ionically implanted into the collector region, prior to growing the silicon germanium epitaxial layer within said base cavity. Extrinsic base regions, comprising areas of the base region which extend laterally beyond the width of said emitter opening, are formed by removing portions of the oxide stack and the nitride layer. Then, boron is ionically implanted into the base region, following the formation of the extrinsic base regions.


REFERENCES:
patent: 5008207 (1991-04-01), Blouse et al.
patent: 5202284 (1993-04-01), Kamins et al.
patent: 5494836 (1996-02-01), Imai
patent: 5506427 (1996-04-01), Imai
patent: 5534713 (1996-07-01), Ismail et al.
patent: 5633179 (1997-05-01), Kamins et al.
patent: 5656514 (1997-08-01), Ahlgren et al.
patent: 5798277 (1998-08-01), Ryum et al.
patent: 6455364 (2002-09-01), Asai et al.
patent: 6504231 (2003-01-01), Kato
patent: 6521974 (2003-02-01), Oda et al.
patent: 6534781 (2003-03-01), Dennison
patent: 0 507 454 (1992-05-01), None
patent: 0 779 652 (1997-08-01), None

Affiliated with

Also associated with

Rating

Method for fabricating heterojunction bipolar transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating heterojunction bipolar transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating heterojunction bipolar transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3175984