Fishing – trapping – and vermin destroying
Patent
1994-12-19
1995-10-17
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 33, 437126, 437128, 437131, 437192, 437196, 437200, 148DIG10, 148DIG11, 148DIG72, 257183, 257191, 257197, H01L 21265
Patent
active
054590841
ABSTRACT:
Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is fully reduced by using a metallic silicide as a base, comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region; growing a collector epitaxial layer on the buried collector region and forming a field oxide layer; selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer and an first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film thereon to form a base electrode thin film; forming a capping oxide layer of about 500 .ANG. thickness only on the base electrode thin film; forming an isolating oxide layer thereon and sequentially and selectively removing the isolating oxide layer, the capping oxide layer, the base electrode thin film and the base layer using a patterned photomask to form a pattern, the isolating oxide layer being provided to electrically isolate base and emitter; forming a side wall oxide layer at both side edges of the pattern; removing a portion of the isolating oxide layer to define an emitter region; forming a passivation layer thereon and selectively removing the passivation layer to form contact holes; and depositing a polysilicon layer doped with impurity ions in the contact holes to form electrodes.
REFERENCES:
patent: 5061646 (1991-10-01), Sivan et al.
patent: 5234846 (1993-08-01), Chu et al.
patent: 5266504 (1993-11-01), Blouse et al.
patent: 5279976 (1994-01-01), Hayden et al.
patent: 5346840 (1994-09-01), Fujioka
patent: 5356821 (1994-10-01), Naruse et al.
Cho Deok-Ho
Han Tae-Hyeon
Kwon Oh-Joon
Lee Soo-Min
Ryum Byung-Ryul
Chaudhuri Olik
Electronics and Telecommunications Research Institute
Korea Telecommunication Authority
Pham Long
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