Method for fabricating field effect transistor structure using s

Details Method for fabricating field effect transistor structure using s Method for fabricating field effect transistor structure using s

1994-06-15

1996-08-06

Fourson, George

Fishing, trapping, and vermin destroying

437 44, H01L 21265

Patent

active

055433375

ABSTRACT:
Four electric field containment regions are formed in a semiconductor substrate by implanting ions into the substrate along four axes that are angularly oriented about a normal to a surface of the substrate in four orthogonal directions respectively. The implant axes are further angularly tilted from the normal by a large angle on the order of 45.degree. such that the axes intersect the normal at a point below the surface. A field effect transistor (FET) is formed in the substrate above the containment regions such that the FET is substantially centered about the normal and has a channel that is aligned with one of the four orthogonal directions. A source and drain are formed at opposite ends of the channel. The containment regions formed under the source and drain respectively are configured to contain electric fields extending therefrom and thereby suppress punchthrough. The four containment regions are implanted at angles that minimize channeling, and any channeling that does occur is symmetrical. A second FET having a channel extending perpendicular to the channel of the first FET can be formed in the substrate over four containment regions that are identical to those for the first FET, thereby enabling universal containment regions to be utilized for FETs of either orientation.

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