Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
1999-10-27
2001-03-13
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C438S643000, C438S250000
Reexamination Certificate
active
06200821
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM); and, more particularly, to a method for fabricating the FeRAM having an interconnection layer for interconnecting a capacitor being in contact with a barrier metal layer and a transistor.
DESCRIPTION OF THE PRIOR ART
A ferroelectric random access memory (FeRAM) is a non-volatile memory to store information without consecutive power supply and studied for a next generation memory device.
In a conventional method for fabricating the FeRAM, aluminum and titanium nitride are used to interconnect a capacitor for storing data and a transistor for switching data input and output. In order to interconnect the capacitor and the transistor, the conventional method uses a metal material, such as aluminum and titanium nitride, as an interconnection material. In a high-temperature process carried out at a temperature of more than 600° C., the metal material as the interconnection material may be melted or conductive characteristics of the metal material may be degraded. Step coverage of the interconnection material may be degraded due to the minimization of a pattern and an aspect ratio of a contact hole increased by high integration. When the metal material is in contact with a junction layer of a transistor, misalignment may be caused. When the distance difference between junction layers is decreased according to the high integration, a junction leakage current may be increased. To address these problems as described above, additional processes such as plug implantation and annealing processes are needed to interconnect the capacitor and the transistor.
Meanwhile, when polysilicon widely used as the interconnection material is employed to interconnect the capacitor and the transistor, the polysilicon reacts with a capacitor electrode material, i.e. platinum, thereby forming platinum (Pt) silicide. At this time, since the characteristics of an electrode of the capacitor are degraded, the characteristics of the capacitor are degraded. Also, since the silicon component of the polysilicon is diffused into a ferroelectric thin film of the electrode of the capacitor, the characteristics of a ferroelectric material may be degraded.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for fabricating a ferroelectric random access memory (FeRAM) that is capable of ensuring step coverage of an interconnection material for interconnecting a ferroelectric capacitor and a transistor.
It is another object of the present invention to provide a method for fabricating a ferroelectric random access memory (FeRAM) that is capable of providing a preferred ohmic contact between an interconnection material and a top electrode of a ferroelectric capacitor.
It is further another object of the present invention to provide a method for fabricating a ferroelectric random access memory (FeRAM) that may improve the characteristics of a ferroelectric capacitor.
In accordance with an aspect of the present invention, there is provided a method for fabricating a ferroelectric random access memory device, comprising the steps of: forming an interlayer insulating layer on a ferroelectric capacitor and a transistor; forming a first opening through the interlayer insulating layer in order to expose a top electrode of the ferroelectric capacitor; forming the barrier metal layer on the resulting structure on which the first opening is formed, wherein the barrier metal layer is in contact with the top electrode of the ferroelectric capacitor; selectively etching the barrier metal and interlayer insulating layers and forming a second opening in order to expose a junction layer of the transistor; forming a polysilicon layer on the resulting structure and doping impurity ions into the polysilicon layer, wherein the doped polysilicon layer is in contact with the junction layer of the transistor; and selectively etching the polysilicon and barrier metal layers, thereby patterning an interconnection layer for interconnecting the transistor and the ferroelectric capacitor, wherein the capacitor is electrically in contact with the interconnection layer via the barrier metal layer and the transistor is electrically in contact with the interconnection layer.
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Blakely & Sokoloff, Taylor & Zafman
Hyundai Electronics Industries Co. UT
Nguyen Tuan H.
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