Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-11-13
2003-08-05
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000
Reexamination Certificate
active
06602721
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric memory device having a capacitor element using a ferroelectric material for a capacitor insulating film and to a method for fabricating the same.
An early-stage ferroelectric memory device that was first mass-produced had a small capacity of about 1 Kbits to 64 Kbits and a planar structure in which the lower electrode is larger in size than the upper electrode. In recent years, however, a device having a large capacity of about 256 Kbits to 4 Mbits and a stacked structure in which the lower electrode is smaller than or equal to the upper electrode has been the main target for development. It has been expected to greatly increase the degree of integration and reliability of a nonvolatile memory device by implementing a ferroelectric memory device having the stacked structure.
An example of a conventional ferroelectric memory device having a stacked structure is disclosed in, e.g., Japanese Patent Laid-Open Publication No. 2000-138349.
As shown in
FIG. 11A
, a capacitor element portion in the conventional ferroelectric memory device is formed above a semiconductor substrate
101
having an impurity diffusion layer
101
a
formed in an upper portion thereof and having an upper surface covered with an interlayer insulating film
102
. A plurality of contact plugs
103
electrically connected to the impurity diffusion layer
101
a
are formed in the interlayer insulating film
102
. A plurality of lower electrodes
104
electrically connected to the contact plugs
103
are buried in a burying insulating film
105
over the interlayer insulating film
102
. The lower electrodes
104
are covered with a capacitor-insulating-film forming film
106
composed of a ferroelectric material and with an upper-electrode forming film
107
, which are patterned subsequently to be opposed to the lower electrodes
104
.
A fabrication method according to the conventional embodiment is characterized in that, to form the capacitor-insulating-film forming film
106
without being affected by the rough configuration of the respective upper surfaces of the interlayer insulating film
102
as an underlying layer and of the lower electrodes
104
, the lower electrodes
104
are buried in the burying insulating film
105
by chemical mechanical polishing (CMP) such that the respective upper surfaces of the lower electrodes
104
and the burying insulating film
105
are planarized. This prevents the occurrence of variations in the thickness of the capacitor-insulating-film forming film
106
when it is formed by spin coating if there is a level difference between the upper surfaces of the lower electrodes
104
and the burying insulating film
105
and thereby provides a ferroelectric memory device with high reliability.
However, the conventional ferroelectric memory device has various problems, which will be described below.
The first problem is that, when the burying insulating film
105
deposited to cover the plurality of lower electrodes
104
is polished by CMP, part of the lower electrodes
104
or of a region to be formed with memory cells is left unpolished to form polishing residue since it is difficult to uniformly expose the lower electrodes
104
over the entire surface of the memory cell formation region.
To solve the first problem, over-polishing is performed to further polish the burying insulating film
105
. As a result of over-polishing, however, the peripheral portions of the upper surfaces of the lower electrodes
104
, which are not the target for polishing, are physically graded off under the pressure exerted during the polishing due to an erosion phenomenon resulting from the different compositions of the adjacent members, i.e., the burying insulating film
105
and the lower electrodes
104
. When the peripheral portions of the lower electrodes
104
that have been once planarized are polished together with the burying insulating film
105
in which the lower electrodes
104
are buried, the upper surface of each of the lower electrodes
104
is inclined so that a so-called recess having a level difference d between the center portion and peripheral portion of the upper surface of the lower electrode is formed. This causes the second problem of the rough upper surfaces of the plurality of lower electrodes
104
.
If over-polishing is performed with respect to the lower electrodes
104
with roughness observed at the upper surfaces thereof, the third problem arises that the lower electrodes
104
peel off from the burying insulating film
105
.
In general, a plurality of memory cells are arranged in rows and columns on a semiconductor substrate. However, since the production yield tends to lower in the peripheral portion of the semiconductor substrate during the fabrication process, dummy electrodes
104
a
are provided on the outer circumferential portion of the semiconductor substrate. As shown in
FIG. 11B
, CMP is also used in the fabrication step for the contact plugs
103
in the step preceding the formation of the lower electrodes
104
. When the CMP process is performed with respect to the contact plugs
103
and the interlayer insulating film
102
, an erosion phenomenon as described above occurs during over-polishing since the members of the contact plugs
103
and the interlayer insulating film
102
have different compositions, so that the thickness of the interlayer insulating film
102
is smaller in a memory-cell main-body region A to be formed with the contact plugs
103
. Specifically, the respective heights of the lower electrodes
104
and the dummy electrodes
104
a
from the semiconductor substrate differ depending on the presence or absence of the contact plugs
103
. This leads to the fourth problem that part of the lower electrodes
104
peels off or remains unpolished to form polishing residue when the lower electrodes
104
and the dummy electrodes
104
a
are planarized. Such peeling off of the lower electrodes
104
from the film or polishing residue causes a bit defect in the ferroelectric memory device. Since the ferroelectric memory devices is a nonvolatile memory device which retains data for a specified period of time and from which the data is read as required, capacitor elements should be formed uniformly for all bits.
As stated previously, variations in the thickness of the interlayer insulating film
102
due to the recess of the lower electrode
104
and the erosion phenomenon of the contact plugs
103
inevitably induce variations in the thickness of the capacitor insulating film
106
. As a result, the data retaining abilities of the individual memory cells are no more equal and the reliability of the memory device is thereby reduced.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide lower electrodes each having a specified configuration during the formation of capacitor elements each having a capacitor insulating film composed of a ferroelectric material, particularly during the formation of the lower electrodes by CMP, by solving the afore-mentioned conventional problems.
To attain the foregoing object, a ferroelectric memory device according to the present invention is so constructed as to positively utilize the erosion phenomenon which occurs during a CMP process performed in the step of forming the contact plugs or the lower electrodes.
Specifically, a first ferroelectric memory device according to the present invention comprises: a plurality of capacitor elements each formed on a semiconductor substrate and composed of a lower electrode, a capacitor insulating film made of a ferroelectric material formed on the lower electrode, and an upper electrode formed on the capacitor insulating film, each of the lower electrodes being buried in a burying insulating film to have an upper surface planarized relative to an upper surface of the burying insulating film and having a plane configuration such that a distance from an arbitrary position on the upper surface of the lower electrode to a nearest end portion thereof is about 0.6 &
Judai Yuji
Kutsunai Toshie
Mikawa Takumi
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Studebaker Donald R.
Tsai Jey
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