Method for fabricating ferroelectric capacitor with improved...

Semiconductor device manufacturing: process – Having magnetic or ferroelectric component

Reexamination Certificate

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Details

C438S240000, C438S396000, C148SDIG003

Reexamination Certificate

active

06238934

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for fabricating a ferroelectric capacitor in ferroelectric memory device, in which an interface surface characteristic is improved and a peeling phenomenon is prevented.
DESCRIPTION OF THE PRIOR ART
A ferroelectric random access memory (FeRAM) is a kind of non-volatile memory device. The FeRAM retains stored data even when a power is removed and its operating speed is comparable to the dynamic random access memory (DRAM). Therefore, the FeRAM is calling attention as the next generation memory device. The FeRAM generally uses ferroelectric materials, such as Sr
x
Bi
y
Ta
2
O
9
(SBT) or Pb (Zr
x
Ti
1−x
)O
3
(PZT), as a ferroelectric layer. An appropriate selection of materials for bottom and top electrodes as well as an appropriate processing control are essential for obtaining an excellent properties of the ferroelectric layer.
In fabricating the ferroelectric capacitor having a Bi-layered perovskite structure, the ferroelectric layer is coated on a bottom electrode, which is typically made of a metal such as Pt, and thereafter a high-temperature thermal treatment is carried out for forming a ferroelectric dielectric medium. The conventional thermal treatment for forming the ferroelectric dielectric medium includes a two-stage process. That is, a RTA (rapid thermal annealing) process is carried out for nucleation in the ferroelectric dielectric medium, and then, a furnace annealing is carried out for a grain growth in the nucleated ferroelectric dielectric medium. Both the RTA process and the furnace annealing are carried out in an O
2
atmosphere at a temperature of 700° C. to 800° C. The typical processing time is 0.5 minutes in the RTA process, and 60 minutes in the furnace annealing process.
Unlike the RTA process which is completed in a short time, the furnace annealing is carried out for a long time at a high temperature, causing a thermally induced mechanical damage. The thermally induced mechanical damage occurs due to the difference between the thermal expansion coefficient of a silicon oxide located under the lower electrode and that of the metallic electrode. This thermally induced mechanical damage weakens the adhesion between the metal and the oxides, with the result that a peeling phenomenon occurs during an etching process after deposition of an upper electrode, thereby decreasing the yield of the device.
Meanwhile, in the ferroelectric layer in which only the nucleation occurs after the RTA process, the interface roughness is not rough, and a dense structure without pores is formed. However, the ferroelectric layer, in which the grain growth occurs after the furnace annealing, shows a high interface roughness and holds numerous pores. Therefore, if an upper electrode is formed on the ferroelectric layer in which the grain growth occurs after the furnace annealing, the interface surface is very severe, and numerous pores are present on the interface between the ferroelectric layer and the upper electrode. As a result, leakage currents are increased and therefore, the ferroelectric capacitor is greatly degraded.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for fabricating a ferroelectric capacitor in ferroelectric memory device, in which an interface characteristic is improved and a peeling phenomenon is prevented.
In accordance with an embodiment of the present invention, there is provided a method for fabricating a ferroelectric capacitor in ferroelectric memory device, comprising the steps of: a) forming a first conductive layer on a semiconductor structure prepared for a formation of the ferroelectric capacitor; b) forming a ferroelectric layer on said first conductive layer; c) carrying out a rapid thermal annealing for nucleation in said ferroelectric layer; d) forming a second conductive layer on said ferroelectric layer; and e) carrying out a thermal treatment for a grain growth in said ferroelectric layer.
In accordance with another embodiment of the present invention, there is provided a method for fabricating a ferroelectric capacitor in a ferroelectric memory device, comprising the steps of: a) forming a first conductive layer on a semiconductor structure prepared for a formation of a ferroelectric capacitor; b) forming a ferroelectric layer having a Bi-layered perovskite structure on said first conductive layer; c) carrying out a rapid thermal annealing for nucleation in said ferroelectric layer; d) forming a second conductive layer on said ferroelectric; e) selectively etching said second conductive layer, said ferroelectric layer and said first conductive layer to form said ferroelectric capacitor; f) carrying out a thermal treatment for compensating damages caused during an etching and for promoting grain growth in said ferroelectric layer; g) forming an interlayer insulating layer, making planarization flow of said interlayer insulating layer, and carrying out a thermal treatment for a grain growth in said ferroelectric layer; and h) etching said interlayer insulating layer to expose said second conductive layer, and carrying out a heat treatment for compensating damages occurred during an etching of said interlayer insulating and for promoting a grain growth in said ferroelectric layer.


REFERENCES:
patent: 5374578 (1994-12-01), Patel et al.
patent: 5728603 (1998-03-01), Emesh et al.
patent: 5751450 (1998-05-01), Robinson
patent: 5886867 (1999-05-01), Chivukula et al.
patent: 7-3431 (1995-06-01), None
patent: 8-339715 (1996-12-01), None
patent: 10-4181 (1998-01-01), None

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