Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-04-18
2003-09-23
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000
Reexamination Certificate
active
06623988
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Korean Application Serial No. 2001-21204 filed Apr. 19, 2001, the entire contents of which are incorporated by reference herein.
DESCRIPTION OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a ferroelectric capacitor of a semiconductor device, whereby a capacitor electrode, which is difficult to handle in a dry etching process, is patterned by a lift-off method using a photoresist mask having a negative slope, thereby ensuring stability in a fabrication process and enabling control of parasitic capacitance.
2. Background of the Invention
With high packing density in semiconductor memory devices such as dynamic random access memories (DRAM), operational characteristics, such as refresh characteristics, are becoming a major issue in semiconductor devices. Accordingly, in order to ensure desired operational characteristics, a technique ensuring sufficient electrostatic capacitance in capacitors has been developed.
Therefore, thin film materials such as SrBi
2
Ta
2
O
9
(SBT) and Pb (ZrxTil-x)O
3
(Lead Zirconium Titanium, PZT) are useful as dielectrics in capacitors of advanced generation semiconductor memory devices and a nonvolatile memory devices, such as ferroelectric random access memory (FERAM).
When SBT is deposited by a coating process, the process is carried out with SBT in gel form. In this case, problems related to partial failure in uniformity may occur, and it is difficult to ensure uniform capacitance of wafers.
An upper electrode of a capacitor is formed with materials identical to those of a lower electrode. Such materials include platinum (Pt), which is highly acid-resistant, and conductive oxides, such as IrO
2
and RuO
2
, or metals, such as Ir and Ru. In a ferroelectric capacitors, SBT films are used mostly as dielectric films and platinum films are used mostly as electrodes.
A related art method for fabricating a ferroelectric capacitor of a semiconductor device will be described with reference to the accompanying drawings.
FIGS. 1A
to
1
J are sectional views illustrating process steps for fabricating a ferroelectric capacitor in the related art.
First, as shown in
FIG. 1A
, a material layer
2
for forming a lower electrode of a capacitor is formed on an oxide film
1
by depositing materials, such as Pt, using a sputtering method.
Then, an SBT film is coated on material layer
2
to form a dielectric layer
3
. Pt is deposited on dielectric layer
3
by a sputtering method to form a material layer
4
for forming an upper electrode.
Subsequently, as shown in
FIG. 1B
, a first photoresist is deposited on material layer
4
and then selectively patterned to form a first mask
5
.
Afterwards, the exposed material layer
4
is selectively etched by a dry etching process, using first mask
5
, to form an upper electrode
4
a.
First mask
5
is then removed.
In addition, as shown in
FIG. 1C
, a second photoresist is deposited on dielectric layer
3
, including upper electrode
4
a.
The second photoresist is then selectively patterned to leave the second photoresist wider than upper electrode
4
a
and surrounding upper electrode
4
a,
so that a second mask
6
is formed.
Exposed dielectric layer
3
is selectively etched using second mask
6
to form a capacitor dielectric layer
3
a.
Second mask
6
is then removed.
Subsequently, as shown in
FIG. 1D
, a third photoresist is deposited on material layer
2
including patterned upper electrode
4
a
and capacitor dielectric layer
3
a.
The third photoresist is then selectively patterned to leave the third photoresist wider than patterned upper electrode
4
a
and capacitor dielectric layer
3
a
and surrounding patterned upper electrode
4
a
and capacitor dielectric layer
3
a,
to form a third mask
7
.
Then, by selectively etching the exposed material layer for forming lower electrode, using third mask
7
, a lower electrode
2
a
is formed. Third mask
7
is then removed.
Additionally, as shown in
FIG. 1E
, a Pre-Metal Dielectric (PMD) layer
8
is formed on the entire surface, and a fourth photoresist is deposited thereon. Then, a capacitor contact region is defined and the fourth photoresist is patterned according to the capacitor contact region to form a fourth mask
9
.
Then, PMD layer
8
is selectively etched using fourth mask
9
to form a first contact hole
10
a
and a second contact hole
10
b.
The first contact hole
10
a
exposes a partial surface of upper electrode
4
a.
Second contact hole
10
b
exposes a partial surface of the lower electrode
2
a.
Fourth mask
9
is then removed.
Subsequently, as shown in
FIG. 1F
, TiN is deposited on a surface of PMD layer
8
, including the bottom surfaces of first contact hole
10
a
and second contact hole
10
b
to form a barrier layer
11
.
As shown in
FIG. 1G
, first contact hole
10
a
and second contact hole
10
b
are masked using a fifth photoresist, and exposed barrier layer
11
is removed to form contact excluding the capacitor forming region.
Furthermore, as shown in
FIG. 1H
, the fifth photoresist is deposited on the entire surface and then selectively patterned to form a fifth mask
13
. An inner line contact hole
14
is then formed using fifth mask
13
.
Then, as shown in
FIG. 11
, multilayered metals consisting of layers of TI, TiN, and W having thickness of 900 Å, 300 Å, and 500 Å respectively are buried within first contact hole
10
a,
second contact hole
10
b,
and inner line contact hole
14
, so that plug layers
15
a,
15
b,
and
15
c
are formed.
Finally, as shown in
FIG. 1J
, multilayered metals consisting of layers of Ti, TiN, and Al having thickness of 100 Å, 150 Å, and 5000 Å, are deposited on the entire surface including plug layers
15
a
,
15
b
, and
15
c
and then selectively patterned by a photolithography process to form metal line layers
16
a,
16
b,
and
16
c.
In related art processes of forming ferroelectric capacitors, a number of masks are separately used when electrodes of the capacitor are formed. In this case, it is difficult to maintain alignment among the different masks.
Therefore to ensure a desired process margin, an area occupied by the capacitor to ensure a process margin may become inefficiently large.
Consequentially, related art methods for fabricating a ferroelectric capacitor have several problems.
One of the problems is that due to the gel form coating of SBT, which is used as a ferroelectric substance, the profile of the SBT is partially unequal. Therefore, it is difficult to maintain the capacitance of an equal wafer level. This is due to typical characteristics of the coating process, whereby a film around the central part of a rotary shaft is thick and as the film nears the edge it becomes thinner.
Another problem is that electrodes are formed through a dry etching process using a photoresist mask. Therefore, due to an unusual electric field peak occurring at edges of the electrodes, it is difficult to distribute charges uniformly.
In addition, due to repeated formation of masks and patterning using the masks, it is difficult to maintain alignment among the different masks.
Furthermore, residues of materials, such as tungsten, remain due to the barrier layer formed at an opening of the contact hole during the formation of plug layers. This may reduce insulating characteristics of the capacitors.
Finally, there may be a degradation of the electrode in relation with the dry etching process during the patterning process of the electrode using Pt, thereby degrading the entire characteristics of a capacitor.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for fabricating a ferroelectric capacitor in a semiconductor device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
The present invention provides a method for fabricating a ferroelectric capacit
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hynix / Semiconductor Inc.
Tsai Jey
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