Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
1999-12-29
2001-04-03
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S006000, C438S253000
Reexamination Certificate
active
06210979
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a ferroelectric random access memory device having ferroelectric capacitors.
DESCRIPTION OF THE PRIOR ART
In general, a titanium (Ti) layer has been widely used for improving adhesive strength between a metal layer and an oxide layer. Also, the Ti layer has been used as a silicide layer for reducing contact resistance in a contact area of a semiconductor device. Also, a TiN layer may be used as a diffusion barrier layer for preventing silicon atoms from being diffused into the Ti layer. Accordingly, in metal wire interconnections of the semiconductor devices, the multi-layer, such as a Ti/TiN layer, is disposed under a metal layer. In the case where this multi-layer is used in connecting a Pt upper electrode of FRAM to an active region of a transistor, the Ti layer formed on the Pt upper electrode may be diffused into a ferroelectric layer through grain boundaries within the Pt layer when a high temperature treatment is carried out in following processes. Particularly, this diffusion deteriorates dielectric characteristics of the SrBi
2
Ta
2
O
9
ferroelectric layer.
On the other hand, in the case of FRAMs using Pt upper electrodes, the adhesive strength between a capping oxide layer, which protects the sidewalls of the upper and lower electrodes and the ferroelectric film, and the Pt upper electrode is reduced. So, at a cleaning process which is carried out after the formation of an interlayer insulating layer, a contact hole and a pattern of the interlayer insulating layer, a lifting may be generated.
Also, when a photoresist layer is used as an etching mask for patterning the Pt layer for the upper electrode, a fence-shaped Pt polymer may be caused and such a polymer is as thick as the photoresist layer. The residue of Pt polymers may not be removed in the following cleaning process and causes processing defects.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an improved method for manufacturing a FRAM device.
It is another object of the present invention to provide a method for preventing Ti atoms from diffusing into a ferroelectric layer of a FRAM device.
It is still another object of the present invention to provide a method for increasing adhesive strength between a capping layer and an upper electrode in a FRAM device and preventing polymers.
In accordance with an aspect of the present invention, there is provided a method for fabricating a FRAM device, comprising the steps of: a) forming a first interlayer insulating layer on a semiconductor device having a transistor; b) forming a first conducting layer, a ferroelectric layer and a second conducting layer on the first interlayer insulating layer; c) forming a TiN layer on the second conducting layer and forming a TiN pattern layer by selectively etching the TiN layer; d) forming an upper electrode by selectively etching the second conducting layer, wherein the second conducting layer is etched using the TiN pattern layer as an etching mask; and e) forming a ferroelectric pattern layer and a lower electrode by selectively etching the ferroelectric layer and the first conducting layer.
In accordance with another aspect of the present invention, there is provided a method for fabricating a FRAM device, comprising the steps of: 1) forming a first interlayer insulating layer on a semiconductor device having a transistor; 2) forming a first conducting layer, a ferroelectric layer and a second conducting layer on the first interlayer insulating layer; 3) forming a TiN layer on the second conducting layer and forming a TiN pattern layer by selectively etching the TiN layer; 4) forming an upper electrode by selectively etching the second conducting layer, wherein the second conducting layer is etched using the TiN pattern layer as an etching mask; 5) forming a ferroelectric pattern layer and a lower electrode by selectively etching the ferroelectric layer and the first conducting layer; 6) transforming the TiN pattern layer to a Ti O
x
(x is 1 to 2) pattern layer by applying thermal treatment to the TiN pattern layer in an O
2
atmosphere; and 7) forming a protecting oxide layer covering an upper portion of the TiO
x
pattern layer and sidewalls of the TiOx pattern layer, the upper electrode, the ferroelectric pattern layer and the lower electrode.
REFERENCES:
patent: 5686323 (1997-11-01), Kataoka
patent: 5940705 (1999-08-01), Lee et al.
patent: 6080617 (2000-06-01), Fujii et al.
Kweon Soon-Yong
Yeom Seung-Jin
Blakely & Sokoloff, Taylor & Zafman
Dang Phuc T.
Hyundai Electronics Industries Co,. Ltd.
Nelms David
LandOfFree
Method for fabricating ferroelectric capacitor improving... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating ferroelectric capacitor improving..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating ferroelectric capacitor improving... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2502678