Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-06-24
2001-08-21
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C710S063000, C710S063000
Reexamination Certificate
active
06277760
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a ferroelectric memory.
2. Background of the Related Art
Currently, there have been wide researches for application of a P(L)ZT or SBT thin film to a memory, such as an FRAM (Ferroelectric Random Access Memory). As a high temperature and an oxygen environment are involved in forming the PZT thin film, metals such as Pt, or oxides such as RuO
2
or IrO
2
, which are stable in an oxygen environment, are widely used as an electrode material. In the fabrication of the FRAM, technologies for forming and etching the electrode and the ferroelectric film are essential. Though there has been researches for dry etching of the PZT thin film or the Pt thin film partly, there have been difficulties in formation of the capacitor for use in the FRAM because present technologies have a low etch rate, a poor etch selectivity to photoresist, and a fence formed at sidewall after an etching. Though there have been researches for fabricating the capacitor using SiO
2
as a mask material for assuring an etch selectivity partly, the assurance of an adequate etch selectivity for fabricating the capacitor for FRAM has been failed(etch selectivity of the Pt film to the SiO
2
is ≈1). Therefore, researches for an appropriate etch mask which can suppress formation of a fence after etching and has an excellent etch selectivity are required.
FIG. 1
illustrates a typical PRAM, which can be fabricated by a process for fabricating a transistor using a CMOS process and a process for fabricating a ferroelectric capacitor. However, as shown in
FIG. 2
, unless CMP(Chemical Mechanical Polishing) is used in fabrication of the transistor using the CMOS process, a great step is formed by a field oxide and a polysilicon. In general, coating of the PZT thin film by sol-gel method is done in spin coating. The spin coating causes a thin film thicker in a grooved portion and thinner in a ridged portion, which causes the following problems when the thin film is etched.
Even after completion of etching the thinner portion of the PZT thin film, a thick PZT film still remains at the thicker portion of the PZT thin film. And, if the film remained at the thicker portion of the PZT thin film is etched, BPSG(Boron Phosphorus Silicate Glass) and an underlying electrode at the thinner portion of the PZT thin film will be also etched seriously. In general, as the BPSG is etched faster than the PZT thin film in a Cl
2
/CF
4
gas environment which is used in etching the PZT thin film, a problem of an excessive etching of the BPSG becomes more serious. Moreover, since a high density device packing leads an etch rate of a groove portion slower than a ridge portion, the problem becomes more serious. For solving the problem, a CMP can be applied before fabrication of the capacitor of the PZT for planarizing the steps after deposition of the BPSG but the CMP costs high and has not established process conditions which are enough for application to a mass production, yet.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for fabricating a ferroelectric capacitor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a ferroelectric capacitor, which has an excellent etch selectivity and can prevent formation of a fence.
Other object of the present invention is to provide a method for fabricating a ferroelectric capacitor, which allows a stable formation of a capacitor regardless of presence of a step.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages in accordance with the purpose of the present invention, as embodied and broadly described, the method for fabricating a ferroelectric capacitor includes the steps of (1) forming an etch stopper a lower electrode, a ferroelectric layer, an upper electrode, and a mask layer in succession on a substrate, (2) patterning the etch mask layer to a required form, (3) using the mask layer as a mask in etching the upper electrode, the ferroelectric layer, and the lower electrode at a time, to expose the etch stopper, and (4) removing the etch stopper and the etch mask layer.
The etch stopper is formed of any one selected from TiO
2
and RuO
2
and the mask layer is formed of any one selected from Ti, Ru and Cr.
The etching in the step (3) is conducted in a Cl
2
/O
2
gas environment, or a Cl
2
, a Cl
2
/CF
4
, and a Cl
2
gas environments in a sequence in etching the upper electrode, the ferroelectric layer, and the lower electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5254217 (1993-10-01), Maniar et al.
patent: 5443688 (1995-08-01), Toure et al.
patent: 5555486 (1996-09-01), Kingon et al.
patent: 5658820 (1997-08-01), Chung
patent: 5840200 (1998-11-01), Nakagawa et al.
patent: 795896 A2 (1997-09-01), None
Kim Dong-Chun
Lee Heon-Min
Nam Hyo-Jin
Fleshner & Kim LLP
LG Electronics Inc.
Umez-Eronini Lynette T.
Utech Benjamin L.
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