Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
1999-02-23
2001-10-09
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C427S376200
Reexamination Certificate
active
06300144
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to the formation of ferro-electric thin films. Particularly PZT thin films are formed using a sol-gel technique. Such ferro-electric films can be used as a dielectric in a ferro-electric capacitor or as a gate insulating layer in a ferro-electric field effect transistor (FET). Both capacitor and FET can be applied in ferro-electric memories for DRAM, FRAM and non-volatile applications.
BACKGROUND OF THE INVENTION
Ferro-electric thin films are used for the fabrication of ferro-electric non-volatile memories. These memories can be stand alone memories as well as embedded memories, e.g. embedded in a conventional CMOS process as used for the fabrication of integrated circuits. Contrary to the conventional floating gate type non-volatile memories, like e.g. flash or EEPROM, ferro-electric non-volatile memories do not need high voltages, i.e. higher than the supply voltage which is defined by the choice of the process wherein these ferro-electric memories are integrated. Consequently, switching at voltages equal to or below the supply voltage has the advantage that no high-voltage generators have to be integrated in said process. Currently, ferro-electric memories using PZT (Lead-Zirconate-Titanate) films require switching voltages from 3 V to 5 V. However due to the ongoing downscaling of the channellength of MOSFETs fabricated in present and future deep submicron CMOS processes, the supply voltage will also further scale down from 3.3V to 2.5V and to 1.5V. Furthermore, ferro-electric memories are also interesting for portable applications due to their low power consumption. For these portable applications, however, the supply voltage should be compatible with single cell battery operation, i.e. operation has to be guaranteed even down to 0.9 V.
One of the methods to deposit a ferro-electric film, e.g. a PZT film, is the sol-gel spin-on technique. Compared with conventional thin film forming processes such as chemical vapour deposition, evaporation or sputtering, a sol-gel technique requires considerably less equipment. Furthermore, throughout different wet chemical methods for the preparation of ceramic oxides, the sol-gel technique offers great advantages because the stoichiometry of the end product can easily be controlled and because it is possible to obtain products for various applications, like e.g. bulk ceramics, fibres, thick coatings or thin films, starting from almost the same precursor solution. In the sol-gel technique, a chemical precursor solution is spin-coated on a substrate, afterwards different thermal treatments are performed for the evaporation of the solvent, the pyrolysis and the crystallization in order to form a ceramic oxide. Particularly, in case a PZT precursor solution is used, a ferro-electric PZT film can be formed. When one wants to produce a high quality ferro-electric film by means of a sol-gel technique, the first requirement is of course a high quality precursor solution, whose characteristics are adapted to the thin film fabrication.
Contrary to SBT (SrBi
2
Ta
2
O
9
) material, where switching at 1.5V is already demonstrated, the fabrication of PZT films on Si substrates showing fully saturated switching at low voltage, i.e. below 3 V, is not yet demonstrated. The most straightforward way of reducing the switching voltage is to decrease the film thickness, provided that this does not deteriorate the electrical characteristics of the films, particularly the value of the remnant polarization P
r
and the rectangularity of the hysteresis loops. The remnant polarization value P
r
determines the signal magnitude for a given capacitor area, and hence defines the minimal capacitor size. On the other hand, a less rectangular or more slanted loop will result in higher switching voltages V
s
which is defined as the amplitude needed to obtain full hysteresis loop opening. However published reports, like K.R. Udayakumar et al., J.Appl.Phys. 77 (8), April 1995, pp. 3981-3986; K. Amanuma et al., Jpn.J.Appl.Phys., Vol. 32 (1993), pp. 4150-4153; L. E. Sanchez et al., Appl. Phys. Lett. 56 (24), June 1990, pp. 2399-2401, on PZT film thickness scaling effects indicate that the electrical characteristics of these films deteriorate if the thickness decreases. Particularly, films which are deposited on Si substrates and use Pt electrodes and which have a reduced film thickness, typically below 200 nm, show a degradation of the electrical characteristics. In particular, one has observed:
a decrease of the remnant polarization, P
r
;
a slanting of the hysteresis loop, i.e. the hysteresis loop becomes less rectangular;
a decrease of breakdown field;
an increase of the coercive field, E
c
.
Consequently, the difference between coercive field and saturation field increases and therefore the magnitude of the saturation field, i.e. the electrical field required to obtain full saturated switching increases even stronger than the magnitude of the coercive field with increasing thickness. Moreover, the minimum film thickness below which the electrical characteristics start to deteriorate, strongly varies with the experimental conditions. This indicates that the observed degradations are not intrinsic but due to the ferro-electric capacitor fabrication process and particularly the process conditions for the formation of a ferro-electric thin film and even more particularly the deposition technique. It is therefore at present not clear, particular when said deposition technique is a sol-gel technique, how to fabricate high quality thickness scaled ferro-electric thin films, particularly for a thickness below 200 nm and more particularly for a thickness below 100 nm.
SUMMARY OF THE INVENTION
In an aspect of the invention a method is disclosed for the formation of ferro-electric films using a multi coating process based on a sol-gel technique. In particular PZT films are formed using a sol-gel technique of an alkoxide-type liquid chemical PZT precursor. The mass fractal dimension of the polymeric structures, where said solution is composed of, has to be sufficiently low, i.e. typically smaller than about 2. Furthermore, hydrolysis steps, used during the preparation of said precursor solution, have to be properly controlled to thereby avoid an increase of the mass fractal dimension of the polymeric structures involved and assuring molecular homogeneity throughout the entire film formation process. Preferably said precursor solution is a Pb(Zr
x
Ti
1−x
)O
3
precursor solution which is prepared, according to an embodiment of the invention, by means of an organic sol-gel technique. Preferably x is in the range from 0.1 to 0.4. Preferably said precursor is diluted in BuEtOH (2-butoxyethanol). Using a more diluted precursor results in thinner coated layers, so in fact the thickness is dependent upon the dilution. According to the present invention, a method for the formation of a ferro-electric film on a substrate is disclosed, comprising the steps of:
a) depositing a ferro-electric layer of a diluted chemical PZT precursor solution on said substrate by means of a sol-gel;
b) evaporating at least the majority of the solvents in said layer by means of a thermal treatment;
c) pyrolysis; and
wherein the sequence of steps a), b) and c) is performed at least twice and thereafter a crystallization step is performed resulting in a film having a remnant polaritization varying less then 30% in said thickness range. The pyrolysis is a thermal treatment, which is typically performed at a temperature in the range from 300 to 500° C. without forming perovskite crystals in said ferro-electric layer. Particularly, a range from 300 to 450° C. can be selected. The thermal treatment of the evaporating step is typically performed at a temperature in the range from 150 to 250° C. Steps a), b) and c) can be performed repeatedly until at least 2 layers and maximum 6 layers are deposited. Finally a crystallization step is performed at temperatures typically at 700 ° C. or below. Particularly said crystallisation step can be a heating step on
Franco Dirk
Maes Herman
Mullens Jules
Norga Gerd
Nouwen Ria
Interuniversitair Micro Elecktronica Centrum (IMEC yzw)
Knobbe Martens Olson & Bear LLP
Rocchegiani Renzo
Smith Matthew
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