Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-05-27
2001-05-15
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000
Reexamination Certificate
active
06232198
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an electrode process. More particularly, the invention relates to a method for fabricating a bottom electrode of a capacitor.
2. Description of the Related Art
As the semiconductor technology being greatly developed, millions of transistors are formed on a chip. Such chip, belongs to an Ultra-Large-Scale Integrated (ULSI) generation, has a need of high speed and access memory capacitance. For this need, techniques of applying a material with a high dielectric constant as a capacitor dielectric layer are greatly developed. For example, a BST ((Ba, Sr)TiO
3
) dielectric material, which has a high dielectric constant and a low film leakage current, is broadly applied to dynamic random access memories (DRAMs) with 4G bits or more access capacitance. Moreover, a noble metal, such as platinum (Pt), is used as an electrode material of capacitors of such memories. Pt has many inherent advantages, such as a low leakage current, a high conductivity and an improvement in problem of a depletion region in a dual-polysilicon capacitor.
Referring to
FIG. 1
, a Pt electrode
108
is shown. The drawing further shows a substrate
100
with a doped area
106
, a dielectric layer
102
having a contact
104
, and a TiN barrier layer
110
over the contact
104
.
The method of fabricating the Pt electrode
108
comprises a step of forming a Pt layer, followed by a photolithography and etching step. As shown in the figure, due to the difficulty in etching the Pt layer, surface area is reduced after being etched. As a consequence, the capacitance of a capacitor based on the Pt electrode
108
is reduced.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating a noble metal electrode. A silicon layer and a solution are provided, wherein the solution has a noble metal complex and a reductant. The silicon layer is immersed in the solution, thereby the silicon layer is displaced by a metal layer. By the displacement from the silicon layer into the metal layer, a metal bottom electrode is formed without suffering from the difficulty in an etching step. Therefore, the disadvantage of reduced surface area can be resolved.
With the optimum surface area of the metal electrode, the inherent advantages for using a noble metal electrode such as high conductivity and low leakage current, and the implementation of a capacitor dielectric layer with a high dielectric constant, a high reliability and performance of devices can be achieved.
In one embodiment of the invention, a dielectric layer is formed to cover a substrate comprising a doped region. A contact coupled to the doped region is formed to penetrate through the dielectric layer. A titanium nitride layer is formed to couple with the contact above the dielectric layer. A silicon layer is formed to cover the titanium nitride layer. The silicon layer is immersed in a solution containing platinum tetrechloride and hydrogen fluoride. A displacement reaction is thus produced. As a result, the titanium nitride layer is covered by a platinum layer serving as a bottom electrode instead of being covered by the silicon layer. An annealing step is performed on the platinum layer to obtain a densified structure thereof.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 5789320 (1998-08-01), Andricacos et al.
Chang Ting-Chang
Liu Po-Tsun
Hoang Quoc
Nelms David
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