Method for fabricating dynamic random access memory cells having

Fishing – trapping – and vermin destroying

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437 60, 437919, H01L 2170, H01L 2700

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active

055019986

ABSTRACT:
A new method for fabricating a microminiature capacitor, on a dynamic random access memory (DRAM) cell, using a single masking level was accomplished. The method involves opening the self-aligned node contact and the area for the bottom electrode of the capacitor, at the same time, using one masking level. The planarization of a low flow temperature glass (BPSG) and an etch back technique is used to define the bottom electrode of the capacitor, which is self-aligned to the etched opening. The resulting capacitor has vertical side walls on the perimeter of the capacitor plate, which increases its area without increasing the lateral area on the DRAM cell. Using one masking level for the fabrication of the capacitor, also eliminates the need to add additional space for the tolerance of a second mask.

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patent: 5155056 (1992-10-01), Jeong-Gyoo
patent: 5185282 (1993-02-01), Lee et al.
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5364811 (1994-11-01), Ajika et al.

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