Method for fabricating DRAM cells having fin-type stacked storag

Details Method for fabricating DRAM cells having fin-type stacked storag Method for fabricating DRAM cells having fin-type stacked storag

1994-09-30

1996-02-13

Fourson, George

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

054911044

ABSTRACT:
An improved method for fabricating dynamic random access memory (DRAM) cell having a fin-shaped capacitor with increased capacitance was achieved. The capacitor is fabricated over the bit lines and makes contact to the source/drain area of a field effect transistor (FET). The capacitor with increased capacitance is formed by depositing an N doped polysilicon layer making electrical contact to the source/drain of the FET. A sacrificial oxide layer is deposited and a contact opening formed over the DRAM cell area to the polysilicon layer. A second polysilicon layer is deposited and patterned over the sacrificial oxide layer forming the top fin portion of the capacitor, which makes electrical contact to the first polysilicon layer through the contact opening. The sacrificial oxide layer is then completely removed by wet etching, while the underlying polysilicon layer provides a very important etch stop to protect the substrate structures. The top fin shaped portion of the capacitor is then used very effectively as a mask to anisotropically etch the bottom polysilicon layer, thereby forming a lower fin structure that is aligned to the top fin structure of the capacitor.

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