Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Isolation by pn junction only
Reexamination Certificate
2002-12-27
2004-02-17
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Isolation by pn junction only
C438S424000, C438S243000, C438S248000
Reexamination Certificate
active
06693018
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a DRAM cell transistor having a trench isolation structure.
2. Description of the Prior Art
A thermally grown silicon oxide film has an action of absorbing boron ions implanted into a silicon substrate. This phenomenon is called a “boron segregation effect”. Thus, in a general MOS transistor having a shallow trench isolation (STI) structure, channel doping concentration is reduced due to the boron segregation effect caused by a field oxide film formed within a trench, as it approaches to the field oxide film. This causes the reduction in effective channel length and the deterioration of a punch-through characteristic.
Hereinafter, the schematic structure of a DRAM cell transistor according to the prior art, and the shortcomings of this DRAM cell transistor, will be described with reference to
FIGS. 1
to
4
.
FIG. 1
is a plan view showing the schematic structure of a DRAM cell transistor according to the prior art.
FIG. 2
is a cross-sectional view taken along the line II—II of
FIG. 1
, which shows the channel doping concentration distribution of a silicon substrate.
FIG. 3
is a graph showing channel doping concentration according to depth, in which Pc and Pe show channel doping concentration according to depth, based on the lines IIIc and IIIe of
FIG. 2
, respectively. Moreover,
FIG. 4
is a cross-sectional view taken along the lines IVc—IVc and IVe—IVe and of
FIG. 1
, in which Jc and Je show the comparison between the lateral profiles of junction regions in the sections taken along the lines IVc—IVc and IVe—IVe of
FIG. 1
, respectively.
As well known, in order to electrically isolate DRAM cell transistors from each other, a trench-shaped field oxide film
14
is formed within a silicon substrate
10
at a fixed region. In order to control the threshold voltage of the transistor, channel ions are implanted into the active region of the silicon substrate
10
, which is defined by the field oxide film
14
. Furthermore, a gate oxide
18
, a gate line
16
and a source/drain junction region
12
are successively formed on the resulting structure.
As described above, the doping concentration caused by the channel ion implantation is reduced due to the boron segregation effect, as it approaches to the field oxide film
14
. Namely, as shown in
FIGS. 2 and 3
, the edge portion of the field oxide film (shown as an A portion in
FIG. 2
) has the reduced channel doping concentration as compared to the central portion of the channel region. Accordingly, as shown in
FIG. 4
, the potential barrier between the channel region and the junction region
12
is lowered at the edge portion of the field oxide film, so that the effective channel length is reduced and the punch-through characteristic is deteriorated.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for fabricating a DRAM cell transistor, by which the electric potential at the edge portion of the field oxide film can be increased, so that the potential barrier between the source/drain junction region and the channel region can be increased and the punch-through characteristic can be improved.
To achieve the above object, the present invention provides a method for fabricating a DRAM cell transistor, in which an electrode structure having the same conductive type as that of a well region is formed within a trench-shaped field oxide film.
According to the present invention, a negative back bias is applied to the well region, and at the same time, also applied to the electrode formed within the field oxide film, so that the electric potential at the edge portion of the field oxide film is increased. Thus, the potential barrier between the junction region and the channel region is increased, thereby improving the punch-through characteristic.
REFERENCES:
patent: 5223447 (1993-06-01), Lee et al.
patent: 6080638 (2000-06-01), Lin et al.
patent: 6103592 (2000-08-01), Levy et al.
patent: 6150686 (2000-11-01), Sugiura et al.
patent: 6228745 (2001-05-01), Wheeler et al.
Kim Hee Sang
Park Sung Kye
Hynix / Semiconductor Inc.
Ladas & Parry
Tsai Jey
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