Method for fabricating double-diffused, lateral transistors

Details Method for fabricating double-diffused, lateral transistors Method for fabricating double-diffused, lateral transistors

1975-04-21

1976-03-23

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

29578, 148175, 148187, 148189, 148190, 357 35, 357 44, 357 50, 357 91, H01L 2126, H01L 21265, H01L 2120

Patent

active

039458571

ABSTRACT:
A double-diffused, lateral transistor structure is fabricated utilizing an etch resistant mask to provide self-aligning positional accuracy for formation of active areas of the transistor. The lateral structure includes semiconductor material having at least one substantially flat surface, and the structure includes at least one region of insulating material formed adjacent the flat surface, the top surface of the insulating material being substantially coplanar with said one surface. A collector is formed in the semiconductor material adjacent first portions of both the flat surface and the insulating material, while an emitter is formed in the semiconductor material adjacent second portions of both the flat surface and the insulating material. A base separates the collector from the emitter.

REFERENCES:
patent: 3328214 (1967-06-01), Hugle
patent: 3411051 (1968-11-01), Kilby
patent: 3524113 (1970-08-01), Agusta et al.
patent: 3575646 (1971-04-01), Karcher
patent: 3648125 (1972-03-01), Peltzer
patent: 3654530 (1972-04-01), Lloyd
patent: 3755001 (1973-08-01), Kooi et al.
patent: 3764396 (1973-10-01), Tarui et al.
patent: 3770516 (1973-11-01), Duffy et al.
zeidenbergs, G., "Lateral PNP . . . Collector," I.B.M. Tech. Discl. Bull., Vol. 14, No. 11, Apr. 1972, p. 3248.

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